LEADER 01394nam 2200373 450 001 996280555203316 005 20231020005623.0 010 $a0-7381-3502-X 035 $a(CKB)1000000000035538 035 $a(NjHacI)991000000000035538 035 $a(EXLCZ)991000000000035538 100 $a20231020d2002 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aIEEE Std 1364.1-2002 $eIEEE Standard for Verilog Register Transfer Level Synthesis /$fInstitute of Electrical and Electronics Engineers (IEEE) 210 1$aNew York :$cInstitute of Electrical and Electronics Engineers (IEEE),$d2002. 215 $a1 online resource (vii, 100 pages) 311 $a0-7381-3501-1 330 $aStandard syntax and semantics for Verilog HDL-based RTL synthesis are described in this standard. 517 $aIEEE Std 1364.1-2002 606 $aVerilog (Computer hardware description language) 606 $aVerilog (Computer hardware description language)$xStandards 615 0$aVerilog (Computer hardware description language) 615 0$aVerilog (Computer hardware description language)$xStandards. 676 $a621.392 801 0$bNjHacI 801 1$bNjHacl 906 $aDOCUMENT 912 $a996280555203316 996 $aIEEE Std 1364.1-2002$93574292 997 $aUNISA