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100   $a20160829d2003      uy              
101 0 $aeng
181   $ctxt
182   $cc
183   $acr
200 10$aInnovative architecture for future generation high-performance processors and systems
210 31$a[Place of publication not identified]$cIEEE Computer Society$d2003
300   $aBibliographic Level Mode of Issuance: Monograph
311   $a0-7695-2019-7 
606   $aComputer architecture$vCongresses
606   $aHigh performance computing$vCongresses
606   $aHigh performance processors$vCongresses
606   $aEngineering & Applied Sciences$2HILCC
606   $aComputer Science$2HILCC
615  0$aComputer architecture
615  0$aHigh performance computing
615  0$aHigh performance processors
615  7$aEngineering & Applied Sciences
615  7$aComputer Science
676   $a004.2/2
702   $aJoe$b Kazuki
702   $aVeidenbaum$b Alex
712 02$aUniversity of California, Irvine.$bCenter for Embedded Computer Systems.
712 12$aInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
801  0$bPQKB
906   $aPROCEEDING
912   $a996214795603316
996   $aInnovative architecture for future generation high-performance processors and systems$92423460
997   $aUNISA