LEADER 05305nam 2200673Ia 450 001 996213952903316 005 20230828231437.0 010 $a1-281-31933-3 010 $a9786611319335 010 $a0-470-76236-5 010 $a0-470-77506-8 010 $a0-470-77758-3 035 $a(CKB)1000000000405415 035 $a(EBL)351468 035 $a(OCoLC)437218715 035 $a(SSID)ssj0000252583 035 $a(PQKBManifestationID)11939296 035 $a(PQKBTitleCode)TC0000252583 035 $a(PQKBWorkID)10180592 035 $a(PQKB)10504792 035 $a(MiAaPQ)EBC351468 035 $a(Au-PeEL)EBL351468 035 $a(CaPaEBR)ebr10236655 035 $a(CaONFJC)MIL131933 035 $a(EXLCZ)991000000000405415 100 $a20060526d2006 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 00$aStructural foundation designers' manual$b[electronic resource] /$fW.G. Curtin ... [et al.] 205 $a2nd ed. /$brev. by N.J. Seward. 210 $aMalden, MA $cBlackwell Pub.$d2006 215 $a1 online resource (390 p.) 300 $aDescription based upon print version of record. 311 $a1-4051-3044-X 320 $aIncludes bibliographical references and index. 327 $aContents; Preface; Preface to First Edition; The Book's Structure and What It Is About; Acknowledgements; Authors' Biographies; Notation; PART 1:APPROACH AND FIRST CONSIDERATIONS; 1 Principles of Foundation Design; 1.1 Introduction; 1.2 Foundation safety criteria; 1.3 Bearing capacity; 1.3.1 Introduction; 1.3.2 Bearing capacity; 1.3.3 Presumed bearing value; 1.3.4 Allowable bearing pressure; 1.3.5 Non-vertical loading; 1.4 Settlement; 1.5 Limit state philosophy; 1.5.1 Working stress design; 1.5.2 Limit state design; 1.6 Interaction of superstructure and soil; 1.6.1 Example 1:Three pinned arch 327 $a1.6.2 Example 2:Vierendeel superstructure1.6.3 Example 3:Prestressed brick diaphragm wall; 1.6.4 Example 4:Composite deep beams; 1.6.5 Example 5:Buoyancy raft; 1.7 Foundation types; 1.7.1 Pad foundations; 1.7.2 Strip footings; 1.7.3 Raft foundations; 1.7.4 Piled foundations; 1.8 Ground treatment (geotechnical processes); 1.9 Changes of soil properties during excavation; 1.10 Post-construction foundation failure; 1.11 Practical considerations; 1.11.1 Example 6:Excavation in waterlogged ground; 1.11.2 Example 7:Variability of ground conditions 327 $a1.11.3 Example 8:Reliability of the soils investigation1.11.4 Example 9:Deterioration of ground exposed by excavation; 1.11.5 Example 10:Effect of new foundation on existing structure; 1.12 Design procedures; 1.13 References; 2 Soil Mechanics,Lab Testing and Geology; A:Soil mechanics; 2.1 Introduction to soil mechanics; 2.2 Pressure distribution through ground; 2.3 Bearing capacity; 2.3.1 Introduction to bearing capacity; 2.3.2 Main variables affecting bearing capacity; 2.3.3 Bearing capacity and bearing pressure; 2.3.4 Determination of ultimate bearing capacity 327 $a2.3.5 Safe bearing capacity - cohesionless soils2.3.6 Safe bearing capacity - cohesive soils; 2.3.7 Safe bearing capacity combined soils; 2.4 Settlement; 2.4.1 Introduction to settlement; 2.4.2 Void ratio; 2.4.3 Consolidation test; 2.4.4 Coefficient of volume compressibility; 2.4.5 Magnitude and rate of settlement; 2.4.6 Settlement calculations; 2.5 Allowable bearing pressure; 2.6 Conclusions; B:Laboratory testing; 2.7 Introduction to laboratory testing; 2.8 Classification (disturbed sample tests); 2.8.1 Particle size and distribution; 2.8.2 Density; 2.8.3 Liquidity and plasticity 327 $a2.8.4 General2.9 Undisturbed sample testing; 2.9.1 Moisture content; 2.9.2 Shear strength; 2.9.3 Consolidation tests (oedometer apparatus); 2.9.4 Permeability tests; 2.9.5 Chemical tests; 2.10 Summary of tests; 2.11 Analysis of results; 2.12 Final observations on testing; C:Geology; 2.13 Introduction to geology; 2.14 Formation of rock types; 2.15 Weathering of rocks; 2.16 Agents of weathering; 2.16.1 Temperature; 2.16.2 Water; 2.16.3 Wind; 2.16.4 Glaciation; 2.17 Earth movement; 2.17.1 Folds,fractures and faults; 2.17.2 Dip and strike; 2.17.3 Jointing; 2.17.4 Drift 327 $a2.18 Errors in borehole interpretation 330 $aThis manual for civil and structural engineers aims to simplify as much as possible a complex subject which is often treated too theoretically, by explaining in a practical way how to provide uncomplicated, buildable and economical foundations. It explains simply, clearly and with numerous worked examples how economic foundation design is achieved. It deals with both straightforward and difficult sites, following the process through site investigation, foundation selection and, finally, design. The book: includes chapters on many aspects of found 606 $aFoundations 606 $aStructural design 615 0$aFoundations. 615 0$aStructural design. 676 $a624.15 701 $aCurtin$b W. G$g(William George)$0991891 701 $aSeward$b N. J$0991892 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a996213952903316 996 $aStructural foundation designers' manual$92270004 997 $aUNISA LEADER 05930nam 2200853Ia 450 001 9910809174903321 005 20250318172315.0 010 $a9786613373892 010 $a9781119995739 010 $a1119995736 010 $a9780470977972 010 $a0470977973 010 $a9781283373890 010 $a1283373890 010 $a9780470977927 010 $a0470977922 010 $a9781119995852 010 $a111999585X 035 $a(CKB)3460000000003457 035 $a(EBL)675308 035 $a(SSID)ssj0000482438 035 $a(PQKBManifestationID)11296392 035 $a(PQKBTitleCode)TC0000482438 035 $a(PQKBWorkID)10526565 035 $a(PQKB)11102905 035 $a(Au-PeEL)EBL675308 035 $a(CaPaEBR)ebr10510475 035 $a(CaONFJC)MIL337389 035 $a(OCoLC)729726229 035 $a(CaSebORM)9780470688472 035 $a(MiAaPQ)EBC675308 035 $a(PPN)242964982 035 $a(OCoLC)810071451 035 $a(OCoLC)ocn810071451 035 $a(Perlego)1014735 035 $a(EXLCZ)993460000000003457 100 $a20101129d2011 uy 0 101 0 $aeng 135 $aurunu||||| 181 $ctxt 182 $cc 183 $acr 200 10$aVHDL for logic synthesis /$fAndrew Rushton 205 $a3rd ed. 210 $aChichester, West Sussex, U.K. $cWiley$d2011 215 $a1 online resource (486 p.) 300 $aDescription based upon print version of record. 311 08$a9780470688472 311 08$a0470688475 320 $aIncludes bibliographical references and index. 327 $aVHDL FOR LOGIC SYNTHESIS; Contents; Preface; List of Figures; List of Tables; 1 Introduction; 1.1 The VHDL Design Cycle; 1.2 The Origins of VHDL; 1.3 The Standardisation Process; 1.4 Unification of VHDL Standards; 1.5 Portability; 2 Register-Transfer Level Design; 2.1 The RTL Design Stages; 2.2 Example Circuit; 2.3 Identify the Data Operations; 2.4 Determine the Data Precision; 2.5 Choose Resources to Provide; 2.6 Allocate Operations to Resources; 2.7 Design the Controller; 2.8 Design the Reset Mechanism; 2.9 VHDL Description of the RTL Design; 2.10 Synthesis Results; 3 Combinational Logic 327 $a3.1 Design Units 3.2 Entities and Architectures; 3.3 Simulation Model; 3.4 Synthesis Templates; 3.5 Signals and Ports; 3.6 Initial Values; 3.7 Simple Signal Assignments; 3.8 Conditional Signal Assignments; 3.9 Selected Signal Assignment; 3.10 Worked Example; 4 Basic Types; 4.1 Synthesisable Types; 4.2 Standard Types; 4.3 Standard Operators; 4.4 Type Bit; 4.5 Type Boolean; 4.6 Integer Types; 4.7 Enumeration Types; 4.8 Multi-Valued Logic Types; 4.9 Records; 4.10 Arrays; 4.11 Aggregates, Strings and Bit-Strings; 4.12 Attributes; 4.13 More on Selected Signal Assignments; 5 Operators 327 $a5.1 The Standard Operators 5.2 Operator Precedence; 5.3 Boolean Operators; 5.4 Comparison Operators; 5.5 Shifting Operators; 5.6 Arithmetic Operators; 5.7 Concatenation Operator; 6 Synthesis Types; 6.1 Synthesis Type System; 6.2 Making the Packages Visible; 6.3 Logic Types - Std_Logic_1164; 6.4 Numeric Types - Numeric_Std; 6.5 Fixed-Point Types - Fixed_Pkg; 6.6 Floating-Point Types - Float_Pkg; 6.7 Type Conversions; 6.8 Constant Values; 6.9 Mixing Types in Expressions; 6.10 Top-Level Interface; 7 Std_Logic_Arith; 7.1 The Std_Logic_Arith Package; 7.2 Contents of Std_Logic_Arith 327 $a7.3 Type Conversions 7.4 Constant Values; 7.5 Mixing Types in Expressions; 8 Sequential VHDL; 8.1 Processes; 8.2 Signal Assignments; 8.3 Variables; 8.4 If Statements; 8.5 Case Statements; 8.6 Latch Inference; 8.7 Loops; 8.8 Worked Example; 9 Registers; 9.1 Basic D-Type Register; 9.2 Simulation Model; 9.3 Synthesis Model; 9.4 Register Templates; 9.5 Register Types; 9.6 Clock Types; 9.7 Clock Gating; 9.8 Data Gating; 9.9 Asynchronous Reset; 9.10 Synchronous Reset; 9.11 Registered Variables; 9.12 Initial Values; 10 Hierarchy; 10.1 The Role of Components; 10.2 Indirect Binding; 10.3 Direct Binding 327 $a10.4 Component Packages 10.5 Parameterised Components; 10.6 Generate Statements; 10.7 Worked Examples; 11 Subprograms; 11.1 The Role of Subprograms; 11.2 Functions; 11.3 Operators; 11.4 Type Conversions; 11.5 Procedures; 11.6 Declaring Subprograms; 11.7 Worked Example; 12 Special Structures; 12.1 Tristates; 12.2 Finite State Machines; 12.3 RAMs and Register Banks; 12.4 Decoders and ROMs; 13 Test Benches; 13.1 Test Benches; 13.2 Combinational Test Bench; 13.3 Verifying Responses; 13.4 Clocks and Resets; 13.5 Other Standard Types; 13.6 Don't Care Outputs; 13.7 Printing Response Values 327 $a13.8 Using TextIO to Read Data Files 330 $aMaking VHDL a simple and easy-to-use hardware description language Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the 517 3 $aVHSIC Hardware Description Language for logic synthesis 606 $aVHDL (Computer hardware description language) 606 $aLogic design$xData processing 606 $aComputer-aided design 615 0$aVHDL (Computer hardware description language) 615 0$aLogic design$xData processing. 615 0$aComputer-aided design. 676 $a621.39/5 686 $aCOM059000$2bisacsh 700 $aRushton$b Andrew$0771816 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910809174903321 996 $aVHDL for logic synthesis$94006985 997 $aUNINA