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100   $a20160829d1995      uy              
101 0 $aeng
135   $aur|||||||||||
181   $ctxt
182   $cc
183   $acr
200 00$aDefect and Fault-Tolerance in VLSI Systems, 1995 Workshop
210 31$a[Place of publication not identified]$cIEEE Computer Society Press$d1995
215   $a1 online resource (320 pages)
300   $aBibliographic Level Mode of Issuance: Monograph
311   $a0-8186-7107-6 
330   $aAn invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield projection and enhancement, fault tolerant and testing techniques, and self-checking and coding techniques. No subject index. Annotation copyright by Book News, Inc., Portland, OR.
606   $aFault-tolerant computing$vCongresses
606   $aIntegrated circuits$xVery large scale integration$xDesign and construction
615  0$aFault-tolerant computing
615  0$aIntegrated circuits$xVery large scale integration$xDesign and construction.
676   $a004.2
801  0$bPQKB
906   $aBOOK
912   $a996210260003316
996   $aDefect and Fault-Tolerance in VLSI Systems, 1995 Workshop$92407799
997   $aUNISA