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101 0 $aeng
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181   $ctxt
182   $cc
183   $acr
200 00$a2006 1st International Symposium on Wireless Pervasive Computing
210 31$a[Place of publication not identified]$cI E E E$d2006
215   $a1 online resource (viii, 584 pages) $cillustrations
300   $aBibliographic Level Mode of Issuance: Monograph
311   $a0-7803-9410-0 
330   $aThis paper presents a new trace-back memory structure for Viterbi decoders that reduces power consumption by 63% compared to the conventional RAM based design. Instead of the intensive read and write operations as required in RAM based designs, the new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly. The structure is used together with appropriate clock and power-aware control signals. Based on a 0.35 /spl mu/m CMOS implementation the trace-back back memory consumes energy of 182 pJ.
606   $aUbiquitous computing$vCongresses
615  0$aUbiquitous computing
676   $a004
712 02$aInstitute of Electrical and Electronics Engineers,
801  0$bPQKB
906   $aPROCEEDING
912   $a996207350803316
996   $a2006 1st International Symposium on Wireless Pervasive Computing$92521896
997   $aUNISA