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100   $a20160829d2005      uy              
101 0 $aeng
181   $ctxt
182   $cc
183   $acr
200 10$a2005 IEEE International Workshop on Memory Technology, Design and Testing : MTDT 2005 : 3-5 August, 2005, Taipei, Taiwan
210 31$a[Place of publication not identified]$cIEEE Computer Society$d2005
300   $aBibliographic Level Mode of Issuance: Monograph
311   $a0-7695-2313-7 
606   $aSemiconductor storage devices$xTesting$vCongresses
606   $aRandom access memory$vCongresses
606   $aElectrical & Computer Engineering$2HILCC
606   $aEngineering & Applied Sciences$2HILCC
606   $aElectrical Engineering$2HILCC
615  0$aSemiconductor storage devices$xTesting
615  0$aRandom access memory
615  7$aElectrical & Computer Engineering
615  7$aEngineering & Applied Sciences
615  7$aElectrical Engineering
676   $a621.39/732
712 02$aGuo li qing hua da xue (Hsinchu, Taiwan)
712 02$aIEEE Computer Society Technical Council on Test Technology.
712 12$aIEEE International Workshop on Memory Technology, Design, and Testing
801  0$bPQKB
906   $aPROCEEDING
912   $a996206157703316
996   $a2005 IEEE International Workshop on Memory Technology, Design and Testing : MTDT 2005 : 3-5 August, 2005, Taipei, Taiwan$92342593
997   $aUNISA