LEADER 01311nam 2200397 450 001 996204373603316 005 20230421041141.0 035 $a(CKB)111026746745286 035 $a(SSID)ssj0000558944 035 $a(PQKBManifestationID)12208279 035 $a(PQKBTitleCode)TC0000558944 035 $a(PQKBWorkID)10565293 035 $a(PQKB)10787867 035 $a(WaSeSS)IndRDA00123992 035 $a(EXLCZ)99111026746745286 100 $a20200529d1997 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$a1997 IEEE International Verilog HDL Conference $eproceedings : March 31-April 3, 1997, Santa Clara, California /$fsponsored by Open Verilog International 210 1$aLos Alamitos, California :$cIEEE Computer Society,$d1997. 215 $a1 online resource (v, 99 pages) 300 $aIncludes index. 311 $a0-8186-7955-7 606 $aVerilog (Computer hardware description language)$vCongresses 615 0$aVerilog (Computer hardware description language) 676 $a621.392 712 02$aOpen Verilog International, 801 0$bWaSeSS 801 1$bWaSeSS 906 $aBOOK 912 $a996204373603316 996 $a1997 IEEE International Verilog HDL Conference$92369733 997 $aUNISA