LEADER 01086cam0-22003851i-450- 001 990000628940403321 005 20051109110322.0 010 $a0-387-94288-2 035 $a000062894 035 $aFED01000062894 035 $a(Aleph)000062894FED01 035 $a000062894 100 $a20020821d1994----km-y0itay50------ba 101 0 $aeng 102 $aUS 105 $aa-------001yy 200 1 $aFast algorithms for 3D-graphics$fGeorg Glaeser 210 $aNew York$cSpringer-Verlag$d1994 215 $axi, 306 p.$cill.$d24 cm$e1 floppy disk 610 0 $aCalcolo matriciale 610 0 $aProgrammazione lineare 610 0 $aCalcolatori elettronici e applicazioni 610 0 $aAlgoritmi per 3d$aGrafica 610 0 $aComputer graphics 676 $a006.67 700 1$aGlaeser,$bGeorg$031804 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990000628940403321 952 $a07 D-142 CNR$b5032$fDINSC 952 $a122-C-29$b13369$fMA1 959 $aDINSC 959 $aMA1 996 $aFast algorithms for 3D-graphics$9315666 997 $aUNINA LEADER 01053nam--2200349---450- 001 990000345840203316 035 $a0034584 035 $aUSA010034584 035 $a(ALEPH)000034584USA01 035 $a0034584 100 $a20010226d1979----km-y0itay0103----ba 101 $aita 102 $aIT 105 $a||||||||001yy 200 1 $a<> progettazione dei circuiti "Phase locked loop (PLL)" con esperimenti 210 $aMilano$cJackson italiana editrice$d1979 215 $a256 p.$cill.$d21 cm 225 2 $aBugbook$v19 410 $12001$aBugbook$v19 461 1$1001-------$12001 676 $a621.3819535 700 1$aBERLIN,$bHoward M.$014628 801 0$aIT$bsalbc$gISBD 912 $a990000345840203316 951 $a001 BUG 19$b10657$c001 BUG$d00100754 959 $aBK 969 $aSCI 979 $aTAMI$b40$c20010226$lUSA01$h1611 979 $c20020403$lUSA01$h1642 979 $aPATRY$b90$c20040406$lUSA01$h1624 996 $aProgettazione dei circuiti "Phase Locked Loop" (PLL), con esperimenti$9332306 997 $aUNISA