LEADER 01966nam--2200529---450- 001 990000337350203316 005 20021203150630.0 010 $a3-540-44143-3 035 $a000033735 035 $aUSA01000033735 035 $a(ALEPH)000033735USA01 035 $a000033735 100 $a20010207d2000----km-y0itay0103----ba 101 $aENG 102 $aDE 105 $a||||||||001yy 200 1 $aIntegrated circuit design$epower and timing modeling, optimization and simulation$e11 International workshop, PATMOS 2000$eTrento,Italy , September , 2000$eproceedings$f...[et al.](eds) 210 $aBerlino$cSpringer-Verlag$dcopyr. 2000 215 $aXVI; 496 p.$cill.$d20 cm 225 2 $aLecture notes in computer science 410 0 $12001$aLecture notes in computer science 461 1$1001-------$12000 610 0 $aCircuiti integralti$xCongressi$z2000 610 0 $aProgettazione assistita da elaboratore$xCongressi$z2001 676 $a621.39 702 1$aSoudris,$bDimitrios 710 12$aInternational workshop, PATMOS 200 <12.; 2000 ;Trento ,Italy >$0542903 801 0$aIT$gISBD 912 $a990000337350203316 951 $a001 LNCS (1918)$bCBS 0025719$c001$d00113325 959 $aBK 969 $aSCI 979 $aTAMI$b40$c20010207$lUSA01$h1559 979 $aTAMI$b40$c20010207$lUSA01$h1603 979 $c20020403$lUSA01$h1641 979 $aDIGIUSEPPE$b90$c20021202$lUSA01$h1616 979 $aDIGIUSEPPE$b90$c20021202$lUSA01$h1617 979 $aDIGIUSEPPE$b90$c20021202$lUSA01$h1706 979 $aDIGIUSEPPE$b90$c20021202$lUSA01$h1713 979 $aDIGIUSEPPE$b90$c20021203$lUSA01$h0923 979 $aDIGIUSEPPE$b90$c20021203$lUSA01$h0926 979 $aDIGIUSEPPE$b90$c20021203$lUSA01$h1504 979 $aDIGIUSEPPE$b90$c20021203$lUSA01$h1505 979 $aDIGIUSEPPE$b90$c20021203$lUSA01$h1506 979 $aPATRY$b90$c20040406$lUSA01$h1624 996 $aIntegrated circuit design$9878030 997 $aUNISA