LEADER 05605nam 2200745Ia 450 001 9910131049403321 005 20200520144314.0 010 $a1-283-40527-X 010 $a9786613405272 010 $a1-119-99114-5 010 $a1-119-99113-7 035 $a(CKB)3460000000003397 035 $a(EBL)699356 035 $a(SSID)ssj0000476978 035 $a(PQKBManifestationID)11324981 035 $a(PQKBTitleCode)TC0000476978 035 $a(PQKBWorkID)10480703 035 $a(PQKB)11377755 035 $a(Au-PeEL)EBL699356 035 $a(CaPaEBR)ebr10510714 035 $a(OCoLC)714797081 035 $a(CaSebORM)9781119992653 035 $a(MiAaPQ)EBC699356 035 $a(EXLCZ)993460000000003397 100 $a20101215d2011 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aESD$b[electronic resource] $edesign and synthesis /$fSteven H. Voldman 205 $a1st edition 210 $aChichester, West Sussex, U.K. $cWiley$d2011 215 $a1 online resource (292 p.) 225 1 $aESD series 300 $aDescription based upon print version of record. 311 $a1-119-99265-6 311 $a0-470-68571-9 320 $aIncludes bibliographical references and index. 327 $aESD Design and Synthesis; Contents; About the Author; Preface; Acknowledgments; 1 ESD Design Synthesis; 1.1 ESD DESIGN SYNTHESIS AND ARCHITECTURE FLOW; 1.1.1 Top-Down ESD Design; 1.1.2 Bottom-Up ESD Design; 1.1.3 Top-Down ESD Design - Memory Semiconductor Chips; 1.1.4 Top-Down ESD Design - ASIC Design System; 1.2 ESD DESIGN - THE SIGNAL PATH AND THE ALTERNATE CURRENT PATH; 1.3 ESD ELECTRICAL CIRCUIT AND SCHEMATIC ARCHITECTURE CONCEPTS; 1.3.1 The Ideal ESD Network and the Current-Voltage DC Design Window; 1.3.2 The ESD Design Window 327 $a1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window1.4 MAPPING SEMICONDUCTOR CHIPS AND ESD DESIGNS; 1.4.1 Mapping Across Semiconductor Fabricators; 1.4.2 ESD Design Mapping Across Technology Generations; 1.4.3 Mapping from Bipolar Technology to CMOS Technology; 1.4.4 Mapping from Digital CMOS Technology to Mixed Signal Analog-Digital CMOS Technology; 1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI); 1.4.6 ESD Design - Mapping CMOS to RF CMOS Technology; 1.5 ESD CHIP ARCHITECTURE, AND ESD TEST STANDARDS; 1.5.1 ESD Chip Architecture and ESD Testing 327 $a1.6 ESD TESTING1.6.1 ESD Qualification Testing; 1.6.2 ESD Test Models; 1.6.3 ESD Characterization Testing; 1.6.4 TLP Testing; 1.7 ESD CHIP ARCHITECTURE AND ESD ALTERNATIVE CURRENT PATHS; 1.7.1 ESD Circuits, I/O, and Cores; 1.7.2 ESD Signal Pin Circuits; 1.7.3 ESD Power Clamp Networks; 1.7.4 ESD Rail-to-Rail Circuits; 1.7.5 ESD Design and Noise; 1.7.6 Internal Signal Path ESD Networks; 1.7.7 Cross-Domain ESD Networks; 1.8 ESD NETWORKS, SEQUENCING, AND CHIP ARCHITECTURE; 1.9 ESD DESIGN SYNTHESIS - LATCHUP-FREE ESD NETWORKS; 1.10 ESD DESIGN CONCEPTS - BUFFERING - INTER-DEVICE 327 $a1.11 ESD DESIGN CONCEPTS - BALLASTING - INTER-DEVICE1.12 ESD DESIGN CONCEPTS - BALLASTING - INTRA-DEVICE; 1.13 ESD DESIGN CONCEPTS - DISTRIBUTED LOAD TECHNIQUES; 1.14 ESD DESIGN CONCEPTS - DUMMY CIRCUITS; 1.15 ESD DESIGN CONCEPTS - POWER SUPPLY DE-COUPLING; 1.16 ESD DESIGN CONCEPTS - FEEDBACK LOOP DE-COUPLING; 1.17 ESD LAYOUT AND FLOORPLAN-RELATED CONCEPTS; 1.17.1 Design Symmetry; 1.17.2 Design Segmentation; 1.17.3 ESD Design Concepts - Utilization of Empty Space; 1.17.4 ESD Design Synthesis - Across Chip Line Width Variation (ACLV); 1.17.5 ESD Design Concepts - Dummy Shapes 327 $a1.17.6 ESD Design Concepts - Dummy Masks1.17.7 ESD Design Concepts - Adjacency; 1.18 ESD DESIGN CONCEPTS - ANALOG CIRCUIT TECHNIQUES; 1.19 ESD DESIGN CONCEPTS - WIRE BONDS; 1.20 DESIGN RULES; 1.20.1 ESD Design Rule Checking (DRC); 1.20.2 ESD Layout vs. Schematic (LVS); 1.20.3 Electrical Resistance Checking (ERC); 1.21 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 ESD Architecture and Floorplanning; 2.1 ESD DESIGN FLOORPLAN; 2.2 PERIPHERAL I/O DESIGN; 2.2.1 Pad-Limited Peripheral I/O Design Architecture; 2.2.2 Pad-Limited Peripheral I/O Design Architecture - Staggered I/O 327 $a2.2.3 Core-Limited Peripheral I/O Design Architecture 330 $aElectrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a 'top-down' design approach. Look inside for extensive coverage 410 0$aESD series. 606 $aSemiconductors$xProtection 606 $aIntegrated circuits$xProtection 606 $aElectrostatics 606 $aAnalog electronic systems$xDesign and construction 615 0$aSemiconductors$xProtection. 615 0$aIntegrated circuits$xProtection. 615 0$aElectrostatics. 615 0$aAnalog electronic systems$xDesign and construction. 676 $a621.3815/2 686 $aTEC008010$2bisacsh 700 $aVoldman$b Steven H$0872423 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910131049403321 996 $aESD$91958013 997 $aUNINA LEADER 02718nam 22006014a 450 001 9910783447203321 005 20230828225705.0 010 $a1-281-12643-8 010 $a9786611126438 010 $a0-8144-2903-3 035 $a(CKB)1000000000241983 035 $a(EBL)242994 035 $a(OCoLC)560032827 035 $a(SSID)ssj0000111427 035 $a(PQKBManifestationID)11137679 035 $a(PQKBTitleCode)TC0000111427 035 $a(PQKBWorkID)10095933 035 $a(PQKB)10869342 035 $a(MiAaPQ)EBC242994 035 $a(Au-PeEL)EBL242994 035 $a(CaPaEBR)ebr10120165 035 $a(CaONFJC)MIL112643 035 $a(OCoLC)935227986 035 $a(EXLCZ)991000000000241983 100 $a20050823d2006 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aBigger isn't always better$b[electronic resource] $ethe new mindset for real business growth /$fRobert M. Tomasko 210 $aNew York $cAMACOM$dc2006 215 $a1 online resource (272 p.) 300 $aDescription based upon print version of record. 311 $a0-8144-0866-4 320 $aIncludes bibliographical references (p. 239-252) and index. 327 $aIs bigger better? -- A bigger stock price is not always a good thing -- Growth is about moving forward -- Are you a fixer or a grower? -- Know where to look -- Know what they want -- Tell the truth -- Create tension to generate forward movement -- Win hearts and minds -- Master momentum and bounce -- Know when to let go, and how to share the wealth. 330 $aWhen it comes to business growth, bigger is not always better. The key to achieving growth is to change the way we think about it. Genuine growth has more to do with reaching maximum potential than reaching maximum size. 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