LEADER 01046nam2 2200253 i 450 001 SUN0013815 005 20070716120000.0 100 $a20030409d1912 |0itac50 ba 101 $aita 102 $aIT 105 $a|||| ||||| 200 1 $aˆ1: La ‰conquista dell'Impero$fGuglielmo Ferrero 210 $aMilano$cFratelli Treves$d1912 215 $a525 p.$d21 cm. 461 1$1001SUN0013805$12001 $aGrandezza e decadenza di Roma$fGuglielmo Ferrero$v1$1210 $aMilano$cFratelli Treves$d1912$1215 $av.$d21 cm. 620 $dMilano$3SUNL000284 700 1$aFerrero$b, Guglielmo$3SUNV010071$067954 712 $aTreves$3SUNV002155$4650 801 $aIT$bSOL$c20181109$gRICA 912 $aSUN0013815 950 $aUFFICIO DI BIBLIOTECA DEL DIPARTIMENTO DI GIURISPRUDENZA$d00 CONS XVIII.Bl.63 (1) $e00 210600568 995 $aUFFICIO DI BIBLIOTECA DEL DIPARTIMENTO DI GIURISPRUDENZA$h210600568$kCONS XVIII.Bl.63 (1)$op$qa 996 $aConquista dell'Impero$91085085 997 $aUNICAMPANIA LEADER 06958nam 2200721 450 001 9910141085303321 005 20230125193911.0 010 $a6613175161 010 $a0-470-82852-8 010 $a1-283-17516-9 010 $a0-470-82850-1 010 $a9786613175168 024 7 $a10.1002/9780470828519 035 $a(CKB)2670000000114767 035 $a(EBL)693370 035 $a(SSID)ssj0000521968 035 $a(PQKBManifestationID)11325856 035 $a(PQKBTitleCode)TC0000521968 035 $a(PQKBWorkID)10527422 035 $a(PQKB)10118608 035 $a(CaBNVSL)mat06016259 035 $a(IDAMS)0b0000648164c992 035 $a(IEEE)6016259 035 $a(Au-PeEL)EBL693370 035 $a(CaPaEBR)ebr10483240 035 $a(CaONFJC)MIL317516 035 $a(CaSebORM)9780470828496 035 $a(MiAaPQ)EBC693370 035 $a(OCoLC)739118465 035 $a(PPN)267015968 035 $a(EXLCZ)992670000000114767 100 $a20151221d2011 uy 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aDesign for embedded image processing on FPGAs /$fDonald G. Bailey 205 $a1st edition 210 1$aNew York, NY :$cWiley,$d2011. 210 2$a[Piscataqay, New Jersey] :$cIEEE Xplore,$d[2011] 215 $a1 online resource (508 p.) 300 $aDescription based upon print version of record. 311 $a0-470-82849-8 311 $a0-470-82851-X 320 $aIncludes bibliographical references and index. 327 $aPreface -- Acknowledgements -- 1 Image Processing -- 1.1 Basic Definitions -- 1.2 Image Formation -- 1.3 Image Processing Operations -- 1.4 Example Application -- 1.5 Real-Time Image Processing -- 1.6 Embedded Image Processing -- 1.7 Serial Processing -- 1.8 Parallelism -- 1.9 Hardware Image Processing Systems -- 2 Field Programmable Gate Arrays -- 2.1 Programmable Logic -- 2.2 FPGAs and Image Processing -- 2.3 Inside an FPGA -- 2.4 FPGA Families and Features -- 2.5 Choosing an FPGA or Development Board -- 3 Languages -- 3.1 Hardware Description Languages -- 3.2 Software-Based Languages -- 3.3 Visual Languages -- 3.4 Summary -- 4 Design Process -- 4.1 Problem Specification -- 4.2 Algorithm Development -- 4.3 Architecture Selection -- 4.4 System Implementation -- 4.5 Designing for Tuning and Debugging -- 5 Mapping Techniques -- 5.1 Timing Constraints -- 5.2 Memory Bandwidth Constraints -- 5.3 Resource Constraints -- 5.4 Computational Techniques -- 5.5 Summary -- 6 Point Operations -- 6.1 Point Operations on a Single Image -- 6.2 Point Operations on Multiple Images -- 6.3 Colour Image Processing -- 6.4 Summary -- 7 Histogram Operations -- 7.1 Greyscale Histogram -- 7.2 Multidimensional Histograms -- 8 Local Filters -- 8.1 Caching -- 8.2 Linear Filters -- 8.3 Nonlinear Filters -- 8.4 Rank Filters -- 8.5 Colour Filters -- 8.6 Morphological Filters -- 8.7 Adaptive Thresholding -- 8.8 Summary -- 9 Geometric Transformations -- 9.1 Forward Mapping -- 9.2 Reverse Mapping -- 9.3 Interpolation -- 9.4 Mapping Optimisations -- 9.5 Image Registration -- 10 Linear Transforms -- 10.1 Fourier Transform -- 10.2 Discrete Cosine Transform -- 10.3 Wavelet Transform -- 10.4 Image and Video Coding -- 11 Blob Detection and Labelling -- 11.1 Bounding Box -- 11.2 Run-Length Coding -- 11.3 Chain Coding -- 11.4 Connected Component Labelling -- 11.5 Distance Transform -- 11.6 Watershed Transform -- 11.7 Hough Transform -- 11.8 Summary -- 12 Interfacing -- 12.1 Camera Input -- 12.2 Display Output. 327 $a12.3 Serial Communication -- 12.4 Memory -- 12.5 Summary -- 13 Testing, Tuning and Debugging -- 13.1 Design -- 13.2 Implementation -- 13.3 Tuning -- 13.4 Timing Closure -- 14 Example Applications -- 14.1 Coloured Region Tracking -- 14.2 Lens Distortion Correction -- 14.3 Foveal Sensor -- 14.4 Range Imaging -- 14.5 Real-Time Produce Grading -- 14.6 Summary -- References -- Index. 330 $aDr Donald Bailey starts with introductory material considering the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The design process for implementing an image processing algorithm on an FPGA is compared with that for a conventional software implementation, with the key differences highlighted. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage is given of a range of low and intermediate level image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques are illustrated with several example applications or case studies from projects or applications the author has been involved with. Issues such as interfacing between the FPGA and peripheral devices are covered briefly, as is designing the system in such a way that it can be more readily debugged and tuned.. Provides a bridge between algorithms and hardware. Demonstrates how to avoid many of the potential pitfalls. Offers practical recommendations and solutions. Illustrates several real-world applications and case studies. Allows those with software backgrounds to understand efficient hardware implementationDesign for Embedded Image Processing on FPGAs is ideal for researchers and engineers in the vision or image processing industry, who are looking at smart sensors, machine vision, and robotic vision, as well as FPGA developers and application engineers.The book can also be used by graduate students studying imaging systems, computer engineering, digital design, circuit design, or computer science. It can also be used as supplementary text for courses in advanced digital design, algorithm and hardware implementation, and digital signal processing and applications.Lecture slides for instructors available at:www.wiley.com/go/bailey/fpga. 606 $aEmbedded computer systems 606 $aField programmable gate arrays 615 0$aEmbedded computer systems. 615 0$aField programmable gate arrays. 676 $a621.39/9 686 $aTEC008070$2bisacsh 700 $aBailey$b Donald G$g(Donald Graeme),$f1962-$0845602 801 0$bCaBNVSL 801 1$bCaBNVSL 801 2$bCaBNVSL 906 $aBOOK 912 $a9910141085303321 996 $aDesign for embedded image processing on FPGAs$91887775 997 $aUNINA LEADER 00966nam0 22002531i 450 001 UON00333311 005 20231205104229.119 100 $a20090924d1950 |0itac50 ba 101 $aeng 102 $aGB 105 $a|||| 1|||| 200 1 $aWhat is a classic$ean address delivered before the Virgil Society on the 16th of October 1944$fT.S. Eliot 210 $aLondon$cFaber and Faber$d1950 215 $a32 p.$d23 cm. 620 $aGB$dLondon$3UONL003044 676 $a824$cLetteratura inglese. Saggi$v21 700 1$aELIOT$bThomas Stearns$3UONV114702$0156602 712 $aFaber and Faber$3UONV246465$4650 801 $aIT$bSOL$c20240220$gRICA 899 $aSIBA - SISTEMA BIBLIOTECARIO DI ATENEO$2UONSI 912 $aUON00333311 950 $aSIBA - SISTEMA BIBLIOTECARIO DI ATENEO$dSI Angl VI A ELI 26 $eSI MR 48639 5 26 996 $aWhat is a classic$91365110 997 $aUNIOR