LEADER 01736 am 22004693u 450 001 9910765811903321 005 20230607231421.0 010 $z9783900305321 (paperback) 035 $a(CKB)2670000000334403 035 $a(SSID)ssj0000985846 035 $a(PQKBManifestationID)11502992 035 $a(PQKBTitleCode)TC0000985846 035 $a(PQKBWorkID)10933309 035 $a(PQKB)11595632 035 $a(WaSeSS)Ind00074248 035 $a(EXLCZ)992670000000334403 100 $a20160829d2001 uy | 101 0 $ager 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$aDamous-el-Karita $edie österreichisch-tunesischen Ausgrabungen der Jahre 1996 und 1997 im Saalbau und der Memoria des Pilgerheiligtumes Damous-el-Karita in Karthago /$fHeimo D Olenz 210 31$aWien :$cÖsterreichisches Archäologisches Institut,$d2001 215 $a1 online resource (253 pages) $cillustrations 225 1 $aSonderschriften. O?sterreichisches Archa?ologisches Institut ;$vBand 35 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$aPrint version: 9783900305321 320 $aIncludes bibliographical references. 410 0$aSonderschriften (O?sterreichisches Archa?ologisches Institut (Vienna, Austria)) ;$vBand 35. 606 $aHistory & Archaeology$2HILCC 606 $aRegions & Countries - Africa$2HILCC 607 $aTunisia$xAntiquities, Roman 615 7$aHistory & Archaeology 615 7$aRegions & Countries - Africa 700 $aDolenz$b Heimo$0674579 702 $aBaldus$b Hans Roland 801 0$bPQKB 801 2$bUkMaJRU 912 $a9910765811903321 996 $aDamous-el-Karita$91283430 997 $aUNINA LEADER 01162nam0 22002651i 450 001 UON00024934 005 20231205102036.107 100 $a20020107d1968 |0itac50 ba 101 $aeng 102 $aGB 105 $a|||| 1|||| 200 1 $aCultural Trends in Medieval India$eArchitecture, Painting, Literature & Language$fH. K. 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P?s?reanu 205 $a1st ed. 2015. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2015. 215 $a1 online resource (XVIII, 469 p. 107 illus.) 225 1 $aTheoretical Computer Science and General Issues,$x2512-2029 ;$v9207 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a3-319-21667-8 327 $aSMT Techniques and Applications -- POLING: SMT Aided Linearizability Proofs -- Finding Bounded Path in Graph Using SMT for Automatic Clock Routing -- Cutting the Mix -- The Inez Mathematical Programming Modulo Theories Framework -- Using Minimal Correction Sets to More Efficiently Compute Minimal Unsatisfiable Sets -- Deciding Local Theory Extensions via E-matching -- HW Verification -- Modular Deductive Verification of Multiprocessor Hardware Designs -- Word-Level Symbolic Trajectory Evaluation -- Verifying Linearizability of Intel® Software Guard Extensions -- Synthesis Synthesis Through Unification -- From Non-preemptive to Preemptive Scheduling Using Synchronization Synthesis -- Counterexample-Guided Quantifier Instantiation for Synthesis in SMT -- Deductive Program Repair -- Quantifying Conformance Using the Skorokhod Metric -- Pareto Curves of Multidimensional Mean-Payoff Games -- Termination -- Conflict-Driven Conditional Termination -- Predicate Abstraction and CEGAR for Disproving Termination ofHigher-Order Functional Programs -- Complexity of Bradley-Manna-Sipma Lexicographic Ranking Functions -- Measuring with Timed Patterns -- Automatic Verification of Stability and Safety for Delay Differential Equations -- Time Robustness in MTL and Expressivity in Hybrid System Falsification -- Concurrency -- Adaptive Concretization for Parallel Program Synthesis -- Automatic Completion of Distributed Protocols with Symmetry -- An Axiomatic Specification for Sequential Memory Models -- Approximate Synchrony: An Abstraction for Distributed Almost-Synchronous Systems -- Automated and Modular Refinement Reasoning for Concurrent Programs. 330 $aThe two-volume set LNCS 9206 and LNCS 9207 constitutes the refereed proceedings of the 27th International Conference on Computer Aided Verification, CAV 2015, held in San Francisco, CA, USA, in July 2015. The total of 58 full and 11 short papers presented in the proceedings was carefully reviewed and selected from 252 submissions. The papers were organized in topical sections named: model checking and refinements; quantitative reasoning; software analysis; lightning talks; interpolation, IC3/PDR, and Invariants; SMT techniques and applications; HW verification; synthesis; termination; and concurrency. 410 0$aTheoretical Computer Science and General Issues,$x2512-2029 ;$v9207 606 $aComputer science 606 $aSoftware engineering 606 $aMachine theory 606 $aComputer engineering 606 $aComputer networks 606 $aComputer Science Logic and Foundations of Programming 606 $aSoftware Engineering 606 $aFormal Languages and Automata Theory 606 $aComputer Engineering and Networks 615 0$aComputer science. 615 0$aSoftware engineering. 615 0$aMachine theory. 615 0$aComputer engineering. 615 0$aComputer networks. 615 14$aComputer Science Logic and Foundations of Programming. 615 24$aSoftware Engineering. 615 24$aFormal Languages and Automata Theory. 615 24$aComputer Engineering and Networks. 676 $a005.14 702 $aKroening$b Daniel$4edt$4http://id.loc.gov/vocabulary/relators/edt 702 $aP?s?reanu$b Corina S$4edt$4http://id.loc.gov/vocabulary/relators/edt 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910484945103321 996 $aComputer Aided Verification$94409985 997 $aUNINA