LEADER 01083nam 2200337 450 001 9910729734003321 005 20230815092528.0 024 7 $a10.5445/KSP/1000155035 035 $a(CKB)5580000000553602 035 $a(NjHacI)995580000000553602 035 $a(EXLCZ)995580000000553602 100 $a20230815d2023 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aSystematic Approaches to Advanced Information Flow Analysis - and Applications to Software Security /$fMartin Mohr 210 1$aKarlsruhe :$cKIT Scientific Publishing,$d2023. 215 $a1 online resource (441 pages) 311 $a1000155035 606 $aSoftware support 615 0$aSoftware support. 676 $a005.16 700 $aMohr$b Martin$01374512 801 0$bNjHacI 801 1$bNjHacl 906 $aBOOK 912 $a9910729734003321 996 $aSystematic Approaches to Advanced Information Flow Analysis - and Applications to Software Security$93421625 997 $aUNINA LEADER 02639oam 2200673zu 450 001 9911020217903321 005 20210731015514.0 010 $a9786610556526 010 $a9781280556524 010 $a1280556528 010 $a9780471457558 010 $a0471457558 010 $a9780470356920 010 $a0470356928 010 $a9780471457565 010 $a0471457566 035 $a(CKB)1000000000019044 035 $a(SSID)ssj0000312670 035 $a(PQKBManifestationID)11229677 035 $a(PQKBTitleCode)TC0000312670 035 $a(PQKBWorkID)10332405 035 $a(PQKB)11500319 035 $a(MiAaPQ)EBC4957239 035 $a(Au-PeEL)EBL4957239 035 $a(CaONFJC)MIL55652 035 $a(OCoLC)65214206 035 $a(CaSebORM)9780471429760 035 $a(OCoLC)840430477 035 $a(OCoLC)ocn840430477 035 $a(EXLCZ)991000000000019044 100 $a20160829d2003 uy 101 0 $aeng 135 $aurunu||||| 181 $ctxt 182 $cc 183 $acr 200 10$aVerilog Coding for Logic Synthesis 205 $a1st edition 210 31$a[Place of publication not identified]$cWiley Interscience Imprint$d2003 215 $a1 online resource (1 v.) $cill 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9780471429760 311 08$a0471429767 320 $aIncludes bibliographical references and index. 327 $aIntroduction -- Asic design flow -- Verilog coding -- Coding style : best-known method for synthesis -- Design example of programmable timer -- Design example of programmable logic block for peripheral interface. 330 $aProvides a practical approach to Verilog design and problem solving. Bulk of the book deals with practical design problems that design engineers solve on a daily basis. Includes over 90 design examples. There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. Book is suitable for use as a textbook in EE departments that have VLSI courses 606 $aDigital electronics 606 $aLogic circuits$xComputer-aided design 606 $aVerilog (Computer hardware description language) 615 0$aDigital electronics. 615 0$aLogic circuits$xComputer-aided design. 615 0$aVerilog (Computer hardware description language) 676 $a621.395 700 $aLee$b Weng Fook$0867193 801 0$bPQKB 906 $aBOOK 912 $a9911020217903321 996 $aVerilog Coding for Logic Synthesis$94417070 997 $aUNINA