LEADER 05562nam 22007094a 450 001 9911019966903321 005 20200520144314.0 010 $a9786610276066 010 $a9781280276064 010 $a1280276061 010 $a9780470092934 010 $a0470092939 010 $a9780470092927 010 $a0470092920 035 $a(CKB)1000000000356540 035 $a(EBL)232704 035 $a(SSID)ssj0000232630 035 $a(PQKBManifestationID)11187742 035 $a(PQKBTitleCode)TC0000232630 035 $a(PQKBWorkID)10214776 035 $a(PQKB)11629175 035 $a(MiAaPQ)EBC232704 035 $a(CaSebORM)9780470092910 035 $a(OCoLC)85820367 035 $a(OCoLC)319836346 035 $a(OCoLC)ocm319836346 035 $a(Perlego)2773896 035 $a(EXLCZ)991000000000356540 100 $a20040630d2005 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aRapidIO $ethe embedded system interconnect /$fSam Fuller with contributions from Alan Gatherer ... [et al.] 210 $aChichester, England ;$aHoboken, NJ $cWiley$dc2005 215 $a1 online resource (384 pages) 300 $aIncludes index. 311 08$a9780470092910 311 08$a0470092912 320 $aIncludes bibliographical references and index. 327 $aRapidIOŽ The Embedded System Interconnect; Contents; Preface; 1 The Interconnect Problem; 1.1 Processor Performance and Bandwidth Growth; 1.2 Multiprocessing; 1.3 System of Systems; 1.4 Problems with Traditional Buses; 1.4.1 Bus Loading; 1.4.2 Signal Skew; 1.4.3 Expense of Wider Buses; 1.4.4 Problems with PCI; 1.5 The Market Problem; 1.6 RapidIO: A New Approach; 1.6.1 Why RapidIO?; 1.7 Where Will it be Used?; 1.8 An Analogy; References; 2 RapidIO Technology; 2.1 Philosophy; 2.2 The Specification Hierarchy; 2.3 RapidIO Protocol Overview; 2.3.1 Packets and Control Symbols; 2.4 Packet Format 327 $a2.5 Transaction Formats and Types2.6 Message Passing; 2.7 Globally Shared Memory; 2.8 Future Extensions; 2.9 Flow Control; 2.9.1 Link Level Flow Control; 2.9.2 End-to-end Flow Control; 2.10 The Parallel Physical Layer; 2.10.1 Parallel Electrical Interface; 2.11 The Serial Physical Layer; 2.11.1 PCS and PMA Layers; 2.11.2 Electrical Interface; 2.12 Link Protocol; 2.13 Maintenance and Error Management; 2.13.1 Maintenance; 2.13.2 System Discovery; 2.13.3 Error Coverage; 2.13.4 Error Recovery; 2.14 Performance; 2.14.1 Packet Structures; 2.14.2 Source Routing and Concurrency 327 $a2.14.3 Packet Overhead2.15 Operation Latency; References; 3 Devices, Switches, Transactions and Operations; 3.1 Processing Element Models; 3.1.1 Integrated Processor-memory Processing Element Model; 3.1.2 Memory-only Processing Element Model; 3.2 I/O Processing Element; 3.3 Switch Processing Element; 3.4 Operations and Transactions; 3.4.1 Operation Ordering; 3.4.2 Transaction Delivery; 3.4.3 Ordered Delivery System Issues; 3.4.4 Deadlock Considerations; 4 I/O Logical Operations; 4.1 Introduction; 4.2 Request Class Transactions; 4.2.1 Field Definitions for Request Class Transactions 327 $a4.3 Response Class Transactions4.3.1 Field Definitions for Response Packet Formats; 4.4 A Sample Read Operation; 4.5 Write Operations; 4.6 Streaming Writes; 4.7 Atomic Operations; 4.8 Maintenance Operations; 4.9 Data Alignment; 5 Messaging Operations; 5.1 Introduction; 5.2 Message Transactions; 5.2.1 Type 10 Packet Format (Doorbell Class); 5.2.2 Type 11 Packet Format (Message Class); 5.2.3 Response Transactions; 5.3 Mailbox Structures; 5.3.1 A Simple Inbox; 5.3.2 An Extended Inbox; 5.3.3 Receiving Messages; 5.4 Outbound Mailbox Structures; 5.4.1 A Simple Outbox; 5.4.2 An Extended Outbox 327 $a5.4.3 Transmitting Messages6 System Level Addressing in RapidIO Systems; 6.1 System Topology; 6.2 Switch-based Systems; 6.3 System Packet Routing; 6.4 Field Alignment and Definition; 6.5 Routing Maintenance Packets; 7 The Serial Physical Layer; 7.1 Packets; 7.1.1 Packet Format; 7.1.2 Packet Protection; 7.1.2.1 Packet CRC Operation; 7.1.2.2 16-Bit Packet CRC Code; 7.2 Control Symbols; 7.2.1 Stype0 Control Symbol Definitions; 7.2.1.1 Packet-accepted Control Symbol; 7.2.1.2 Packet-retry Control Symbol; 7.2.1.3 Packet-not-accepted Control Symbol; 7.2.1.4 Status Control Symbol 327 $a7.2.1.5 Link-response Control Symbol 330 $aRapidIO - The Embedded System Interconnect brings together one essential volume on RapidIO interconnect technology, providing a major reference work for the evaluation and understanding of RapidIO. Covering essential aspects of the specification, it also answers most usage questions from both hardware and software engineers. It will also serve as a companion text to the specifications when developing or working with the RapidIO interconnect technology. Including the history of RapidIO and case of studies of RapidIO deployment, this really is the definitive reference guide for this new area of 606 $aInterconnects (Integrated circuit technology) 606 $aEmbedded computer systems 615 0$aInterconnects (Integrated circuit technology) 615 0$aEmbedded computer systems. 676 $a621.3815 700 $aFuller$b Samuel H.$f1946-$025956 701 $aGatherer$b Alan$01838147 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9911019966903321 996 $aRapidIO$94418243 997 $aUNINA