LEADER 04253nam 2200649Ia 450 001 9911007371003321 005 20200520144314.0 010 $a1-282-15174-6 010 $a9786612151743 010 $a1-61583-318-8 010 $a1-84919-020-8 035 $a(CKB)1000000000704001 035 $a(EBL)445613 035 $a(OCoLC)505868906 035 $a(SSID)ssj0000310929 035 $a(PQKBManifestationID)12068199 035 $a(PQKBTitleCode)TC0000310929 035 $a(PQKBWorkID)10290172 035 $a(PQKB)10999732 035 $a(MiAaPQ)EBC445613 035 $a(EXLCZ)991000000000704001 100 $a20051122d2006 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 00$aSystem-on-chip $enext generation electronics /$fedited by Bashir M. Al-Hashimi 210 $aLondon $cInstitution of Electrical Engineers$dc2006 215 $a1 online resource (940 p.) 225 1 $aIEE circuits, devices and systems series ;$v18 300 $aDescription based upon print version of record. 311 $a0-86341-552-0 320 $aIncludes bibliographical references and index. 327 $aContents; PART I - System-level design; 1 Multi-criteria decision making in embedded system design; 2 System-level performance analysis - the SymTA/S approach; 3 Analysis and optimisation of heterogeneous real-time embedded systems; 4 Hardware/software partitioning of operating systems: focus on deadlock avoidance; Models of computation in the design process; 6 Architecture description languages for programmable embedded systems; PART II -Embedded software; 7 Concurrent models of computation for embedded software; 8 Retargetable compilers and architecture exploration for embedded processors 327 $a9 Software power optimisationPART III -Power reduction and management; 10 Power-efficient data management for dynamic applications; 11 Low power system scheduling, synthesis and displays; 12 Power minimisation techniques at the RT-level and below; 13 Leakage power analysis and reduction for nano-scale circuits; PART IV - Reconfigurable computing; 14 Reconfigurable computing: architectures and design methods; PART V-Architectural synthesis; 15 CAD tools for embedded analogue circuits in mixed-signal integrated Systems-on-Chip; 16 Clock-less circuits and system synthesis 327 $aPART VI - Network-on-chip17 Network-on-chip architectures and design methods; 18 Asynchronous on-chip networks; PART VII -Simulation and verification; 19 Covalidation of complex hardware/software systems; 20 Hardware/software cosimulation from interface perspective; 21 System-level validation using formal techniques; PART VIII - Manufacturing test; 22 Efficient modular testing and test resource partitioning for core-based SoCs; 23 On-chip test infrastructure design for optimal multi-site testing; 24 High-resolution flash time-to-digital conversion and calibration for system-on-chip testing 327 $a25 Yield and reliability prediction forDSM circuits 330 $aSystem-on-Chip (SoC) represents the next major market for microelectronics, and there is considerable interest world-wide in developing effective methods and tools to support the SoC paradigm. SoC is an expanding field, at present the technical and technological literature about the overall state-of-the-art in SoC is dispersed across a wide spectrum which includes books, journals, and conference proceedings.The book provides a comprehensive and accessible source of state-of-the-art information on existing and emerging SoC key research areas, provided by leading experts in th 410 0$aIEE circuits, devices and systems series ;$v18. 606 $aSystems on a chip 606 $aEmbedded computer systems 606 $aMicroelectronics 615 0$aSystems on a chip. 615 0$aEmbedded computer systems. 615 0$aMicroelectronics. 676 $a621.381 676 $a621.395 701 $aAl-Hashimi$b Bashir$09560 712 02$aInstitution of Electrical Engineers. 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9911007371003321 996 $aSystem-on-chip$94389775 997 $aUNINA