LEADER 03772nam 22006252 450 001 9911006654403321 005 20151005020623.0 010 $a1-107-17882-7 010 $a1-280-91713-X 010 $a9786610917136 010 $a0-511-32232-1 010 $a0-511-28972-3 010 $a0-511-29032-2 010 $a0-511-28841-7 010 $a1-60119-729-2 010 $a0-511-54111-2 010 $a0-511-28909-X 035 $a(CKB)1000000000352041 035 $a(EBL)311253 035 $a(OCoLC)173812628 035 $a(SSID)ssj0000071379 035 $a(PQKBManifestationID)11110103 035 $a(PQKBTitleCode)TC0000071379 035 $a(PQKBWorkID)10071400 035 $a(PQKB)11118630 035 $a(UkCbUP)CR9780511541117 035 $a(MiAaPQ)EBC311253 035 $a(PPN)261309390 035 $a(EXLCZ)991000000000352041 100 $a20090501d2007|||| uy| 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aAdvanced model order reduction techniques in VLSI design /$fSheldon X.-D. Tan, Lei He 210 1$aCambridge :$cCambridge University Press,$d2007. 215 $a1 online resource (xviii, 240 pages) $cdigital, PDF file(s) 300 $aTitle from publisher's bibliographic system (viewed on 05 Oct 2015). 311 08$a1-107-41154-8 311 08$a0-521-86581-6 320 $aIncludes bibliographical references and index. 327 $aList of figures; List of tables; Preface; 1. Introduction; 2. Projection-based model order reduction algorithms; 3. Truncated balanced realization methods for model order reduction; 4. Passive balanced truncation of linear systems in descriptor form; 5. Passive hierarchical model order reduction; 6. Terminal reduction of linear dynamic circuits; 7. Vector potential equivalent circuit for inductance modeling; 8. Structure-preserving model order reduction; 9. Block structure-preserving reduction for RLCK circuits; 10. Model optimization and passivity enforcement; 11. General multi-port circuit realization; 12. Model order reduction for multi-terminal linear dynamic circuits; 13. Passive modeling by signal waveform shaping; References; Index. 330 $aModel order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This 2007 book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry. 606 $aIntegrated circuits$xVery large scale integration$xDesign 615 0$aIntegrated circuits$xVery large scale integration$xDesign. 676 $a621.395 700 $aTan$b Sheldon X. D.$01822127 702 $aHe$b Lei 801 0$bUkCbUP 801 1$bUkCbUP 906 $aBOOK 912 $a9911006654403321 996 $aAdvanced model order reduction techniques in VLSI design$94388192 997 $aUNINA