LEADER 03451nam 22006614a 450 001 9911006647203321 005 20200520144314.0 010 $a1-107-16031-6 010 $a1-280-74962-8 010 $a9786610749621 010 $a0-511-26247-7 010 $a0-511-26486-0 010 $a0-511-26558-1 010 $a0-511-26328-7 010 $a0-511-33160-6 010 $a0-511-60705-9 010 $a0-511-26409-7 035 $a(CKB)1000000000353330 035 $a(EBL)283578 035 $a(OCoLC)476030602 035 $a(SSID)ssj0000137375 035 $a(PQKBManifestationID)11129800 035 $a(PQKBTitleCode)TC0000137375 035 $a(PQKBWorkID)10088338 035 $a(PQKB)10157330 035 $a(UkCbUP)CR9780511607059 035 $a(MiAaPQ)EBC283578 035 $a(PPN)261320270 035 $a(EXLCZ)991000000000353330 100 $a20040701d2005 uy 0 101 0 $aeng 135 $aur||||||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aDesigning digital computing systems with Verilog /$fDavid J. Lilja and Sachin S. Sapatnekar 210 $aCambridge ;$aNew York $cCambridge University Press$d2005 215 $a1 online resource (ix, 160 pages) $cdigital, PDF file(s) 300 $aTitle from publisher's bibliographic system (viewed on 05 Oct 2015). 311 $a0-521-04572-X 311 $a0-521-82866-X 320 $aIncludes bibliographical references and index. 327 $aCover; Half-title; Title; Copyright; Contents; Preface; 1 Controlling complexity; 2 A Verilogical place to start; 3 Defining the instruction set architecture; 4 Algorithmic behavioral modeling; 5 Building an assembler for VeSPA; 6 Pipelining; 7 Implementation of the pipelined processor; 8 Verification; APPENDIX A The VeSPA instruction set architecture (ISA); APPENDIX B The VASM assembler; Index 330 $aThis book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers. 606 $aVerilog (Computer hardware description language) 606 $aElectronic digital computers$xDesign and construction 615 0$aVerilog (Computer hardware description language) 615 0$aElectronic digital computers$xDesign and construction. 676 $a621.39/2 700 $aLilja$b David J$01825436 701 $aSapatnekar$b Sachin S.$f1967-$01825437 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9911006647203321 996 $aDesigning digital computing systems with Verilog$94393116 997 $aUNINA