LEADER 05765nam 2200781 a 450 001 9911006627103321 005 20200520144314.0 010 $a9786611370947 010 $a9781281370945 010 $a1281370940 010 $a9780080558288 010 $a0080558283 035 $a(CKB)1000000000400072 035 $a(EBL)349545 035 $a(OCoLC)476166348 035 $a(SSID)ssj0000076889 035 $a(PQKBManifestationID)11107431 035 $a(PQKBTitleCode)TC0000076889 035 $a(PQKBWorkID)10014425 035 $a(PQKB)10357093 035 $a(MiAaPQ)EBC349545 035 $a(CaSebORM)9780123738929 035 $a(PPN)271205857 035 $a(OCoLC)435501529 035 $a(OCoLC)ocn435501529 035 $a(OCoLC)ocn435501529 035 $a(EXLCZ)991000000000400072 100 $a20080130d2008 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aOn-chip communication architectures $esystem on chip interconnect /$fSudeep Pasricha, Nikil Dutt 205 $a1st edition 210 $aAmsterdam ;$aBoston $cElsevier / Morgan Kaufmann Publishers$dc2008 215 $a1 online resource (541 p.) 225 1 $aSystems on Silicon 300 $aDescription based upon print version of record. 311 08$a9780123738929 311 08$a012373892X 320 $aIncludes bibliographical references and index. 327 $aFront Cover; On-Chip Communication Architectures: System on Chip Interconnect; Copyright Page; Contents; Preface; About the Authors; Acknowledgments; List of Contributors; CHAPTER 1 Introduction; 1.1. Trends in System-On-Chip Design; 1.2. Coping with Soc Design Complexity; 1.3. ESL Design Flow; 1.4. On-Chip Communication Architectures: A Quick Look; 1.5. Book Outline; CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures; 2.1. Terminology; 2.2. Characteristics of Bus-Based Communication Architectures; 2.3. Data Transfer Modes; 2.4. Bus Topology Types 327 $a2.5. Physical Implementation of Bus Wires2.6. Discussion: Buses in the DSM Era; 2.7. Summary; CHAPTER 3 On-Chip Communication Architecture Standards; 3.1. Standard On-Chip Bus-Based Communication Architectures; 3.2. Socket-Based On-Chip Bus Interface Standards; 3.3. Discussion: Off-Chip Bus Architecture Standards; 3.4. Summary; CHAPTER 4 Models for Performance Exploration; 4.1. Static Performance Estimation Models; 4.2. Dynamic (Simulation-Based) Performance Estimation Models; 4.3. Hybrid Communication Architecture Performance Estimation Approaches; 4.4. Summary 327 $aCHAPTER 5 Models for Power and Thermal Estimation5.1. Bus Wire Power Models; 5.2. Comprehensive Bus Architecture Power Models; 5.3. Bus Wire Thermal Models; 5.4. Discussion: PVT Variation-Aware Power Estimation; 5.5. Summary; CHAPTER 6 Synthesis of On-Chip Communication Architectures; 6.1. Bus Topology Synthesis; 6.2. Bus Protocol Parameter Synthesis; 6.3. Bus Topology and Protocol Parameter Synthesis; 6.4. Physical Implementation Aware Synthesis; 6.5. Memory-Communication Architecture Co-synthesis; 6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures 327 $a6.7. SummaryCHAPTER 7 Encoding Techniques for On-Chip Communication Architectures; 7.1. Techniques for Power Reduction; 7.2. Techniques for Reducing Capacitive Crosstalk Delay; 7.3. Techniques for Reducing Power and Capacitive Crosstalk Effects; 7.4. Techniques for Reducing Inductive Crosstalk Effects; 7.5. Techniques for Fault Tolerance and Reliability; 7.6. Summary; CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design; 8.1. Split Bus Architectures; 8.2. Serial Bus Architectures; 8.3. CDMA-Based Bus Architectures; 8.4. Asynchronous Bus Architectures 327 $a8.5. Dynamically Reconfigurable Bus Architectures8.6. Summary; CHAPTER 9 On-Chip Communication Architecture Refinement and Interface Synthesis; 9.1. On-Chip Communication Architecture Refinement; 9.2. Interface Synthesis; 9.3. Discussion: Interface Synthesis; 9.4. Summary; CHAPTER 10 Verification and Security Issues in On-Chip Communication Architecture Design; 10.1. Verification of On-Chip Communication Protocols; 10.2. Compliance Verification for IP Block Integration; 10.3. Basic Concepts of SoC Security; 10.4. Security Support in Standard Bus Protocols 327 $a10.5. Communication Architecture Enhancements for Improving SoC Security 330 $aOver the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains 410 0$aSystems on Silicon 606 $aSystems on a chip 606 $aMicrocomputers$xBuses 606 $aComputer architecture 606 $aInterconnects (Integrated circuit technology) 615 0$aSystems on a chip. 615 0$aMicrocomputers$xBuses. 615 0$aComputer architecture. 615 0$aInterconnects (Integrated circuit technology) 676 $a621.3815 700 $aPasricha$b Sudeep$01372957 701 $aDutt$b Nikil$01822709 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9911006627103321 996 $aOn-chip communication architectures$94389053 997 $aUNINA