LEADER 06000nam 2200781 a 450 001 9910971902703321 005 20251116203324.0 010 $a1-281-10004-8 010 $a9786611100049 010 $a0-08-055680-9 035 $a(CKB)1000000000408431 035 $a(EBL)330094 035 $a(OCoLC)437198372 035 $a(SSID)ssj0000078265 035 $a(PQKBManifestationID)11110472 035 $a(PQKBTitleCode)TC0000078265 035 $a(PQKBWorkID)10065429 035 $a(PQKB)11246940 035 $a(MiAaPQ)EBC330094 035 $a(CaSebORM)9780123739735 035 $a(Au-PeEL)EBL330094 035 $a(CaPaEBR)ebr10203465 035 $a(CaONFJC)MIL110004 035 $a(OCoLC)435501530 035 $a(OCoLC)ocn435501530 035 $a(FI-CZ)9780123739735 035 $a(EXLCZ)991000000000408431 100 $a20070604d2008 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 00$aSystem-on-chip test architectures $enanometer design for testability /$fedited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba 205 $a1st ed. 210 $aAmsterdam ;$aBoston $cMorgan Kaufmann Publishers$dc2008 210 1$cElsevier$d[2007] 215 $a1 online resource (893 p.) 225 1 $aThe Morgan Kaufmann series in systems on silicon 300 $aDescription based upon print version of record. 311 08$a0-12-373973-X 320 $aIncludes bibliographical references and index. 327 $aFront Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard) 327 $a1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures 327 $a2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST 327 $a2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction 327 $a2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability 327 $a3.2.4 Availability 330 $aModern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master qu 410 0$aMorgan Kaufmann series in systems on silicon. 606 $aSystems on a chip$xTesting 606 $aIntegrated circuits$xVery large scale integration$xTesting 606 $aIntegrated circuits$xVery large scale integration$xDesign 615 0$aSystems on a chip$xTesting. 615 0$aIntegrated circuits$xVery large scale integration$xTesting. 615 0$aIntegrated circuits$xVery large scale integration$xDesign. 676 $a621.39/5 700 $aWang$b Laung-Terng$01856669 701 $aWang$b Laung-Terng$01856669 701 $aStroud$b Charles E$01856670 701 $aTouba$b Nur A$01856671 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910971902703321 996 $aSystem-on-chip test architectures$94456318 997 $aUNINA LEADER 03025nam 22006133u 450 001 9911102917203321 005 20260720113601.0 010 $a0-8173-8660-2 035 $a(CKB)2550000001142819 035 $a(EBL)1389432 035 $a(OCoLC)858763346 035 $a(SSID)ssj0001054234 035 $a(PQKBManifestationID)11577909 035 $a(PQKBTitleCode)TC0001054234 035 $a(PQKBWorkID)11126580 035 $a(PQKB)10632675 035 $a(MiAaPQ)EBC1389432 035 $a(EXLCZ)992550000001142819 100 $a20131216d2014|||| u|| | 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt 182 $cc 183 $acr 200 10$aIn the Name of Necessity $eMilitary Tribunals and the Loss of American Civil Liberties 205 $a1st ed. 210 $aTuscaloosa $cUniversity of Alabama Press$d2014 215 $a1 online resource (327 p.) 225 1 $aAlbma Rhetoric Cult & Soc Crit 300 $aDescription based upon print version of record. 311 08$a0-8173-1475-X 311 08$a9780817357382 327 $aContents; Acknowledgments; 1. Introduction: The Genealogical Origins of Necessity and Military Necessity; 2. The Capture of Major Andre?; 3. Cultural Amnesias and Legal Recollections: Forgetting and Remembering the 1862 U.S.-Dakota War Tribunals; 4. Abraham Lincoln and Ex Parte Milligan; 5. The Military Trial of Major Henry Wirz; 6. FDR, Wartime Anxieties, and the Saboteurs' Case; 7. General MacArthur's Tribunal and the Trial of General Yamashita; 8. The Legal and Public Debates over the Necessity of Bush's Military Order; 9. The Future Use of Military Tribunals; Notes; Bibliography; Index 330 $aAnalyses the ways American leaders have justified the use of military tribunals, the suspension of due process, and the elimination of habeas corpus. Though the war on terrorism is said to have generated unprecedented military situations, arguments for the Patriot Act and military tribunals following 9/11 resemble many historical claims for restricting civil liberties, more often than not in the name of necessity. Marouf Hasian Jr. examines the major legal cases that show how various generations have represented the need for military tribunals, and how officials 410 0$aAlbma Rhetoric Cult & Soc Crit 606 $aCivil rights -- United States 606 $aCourts-martial and courts of inquiry -- United States 606 $aMilitary necessity 606 $aNecessity (Law) -- United States 615 4$aCivil rights -- United States. 615 4$aCourts-martial and courts of inquiry -- United States. 615 4$aMilitary necessity. 615 4$aNecessity (Law) -- United States. 676 $a343.73 676 $a343.73/0143 676 $a343.730143 700 $aHasian$b Marouf Arif$cJr.$0867031 801 0$bAU-PeEL 801 1$bAU-PeEL 801 2$bAU-PeEL 906 $aBOOK 912 $a9911102917203321 996 $aIn the Name of Necessity$94682327 997 $aUNINA