LEADER 03980nam 2200661Ia 450 001 9910966669803321 005 20200520144314.0 010 $a9781596933842 010 $a1596933844 035 $a(CKB)1000000000787510 035 $a(EBL)456885 035 $a(OCoLC)503447788 035 $a(SSID)ssj0000137235 035 $a(PQKBManifestationID)11144685 035 $a(PQKBTitleCode)TC0000137235 035 $a(PQKBWorkID)10087805 035 $a(PQKB)10699572 035 $a(Au-PeEL)EBL456885 035 $a(CaPaEBR)ebr10312962 035 $a(OCoLC)535923707 035 $a(CaBNVSL)mat09100660 035 $a(IEEE)9100660 035 $a(MiAaPQ)EBC456885 035 $a(Perlego)4667991 035 $a(EXLCZ)991000000000787510 100 $a20090117d2009 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aDesign methodology for RF CMOS phase lock loops /$fCarlos Quemada, Guillermo Bistue, Inigo Adin 205 $a1st ed. 210 $aBoston ;$aLondon $cArtech House$dc2009 215 $a1 online resource (242 p.) 225 1 $aArtech House microwave library 300 $aDescription based upon print version of record. 311 08$a9781596933835 311 08$a1596933836 320 $aIncludes bibliographical references and index. 327 $aDesign Methodology for RF CMOS Phase Locked Loops; Contents; Preface; 1 Approach to CMOS PLL Design; 2 PLL Fundamentals; 3 LC-Tank Integrated Oscillators; 4 Frequency Divider; 5 Phase Frequency Detector/Phase Detector; 6 Determination of Building Blocks Specifications; 7 Design of a 3.2-GHz CMOS VCO; 8 Design of a Frequency Divider; 9 Design of a Phase Frequency Detector; 10 Design of the Complete PLL; 11 PLL Characterization and Results; About the Authors; Index 330 3 $aBlast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications.$cPublisher abstract. 410 0$aArtech House microwave library. 606 $aMetal oxide semiconductors, Complementary$xDesign and construction 606 $aPhase-locked loops$xDesign and construction 615 0$aMetal oxide semiconductors, Complementary$xDesign and construction. 615 0$aPhase-locked loops$xDesign and construction. 676 $a621.3815/364 700 $aQuemada$b Carlos$01812998 701 $aAdin$b IInigoigo$01812999 701 $aBistue$b Guillermo$01813000 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910966669803321 996 $aDesign methodology for RF CMOS phase lock loops$94365723 997 $aUNINA