LEADER 05212nam 2200601 a 450 001 9910876805703321 005 20200520144314.0 010 $a1-281-31816-7 010 $a9786611318161 010 $a0-470-51617-8 010 $a0-470-51616-X 035 $a(CKB)1000000000402600 035 $a(EBL)351244 035 $a(OCoLC)437218528 035 $a(SSID)ssj0000189511 035 $a(PQKBManifestationID)11173130 035 $a(PQKBTitleCode)TC0000189511 035 $a(PQKBWorkID)10156684 035 $a(PQKB)10812975 035 $a(MiAaPQ)EBC351244 035 $a(EXLCZ)991000000000402600 100 $a20071015d2007 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aLatchup /$fSteven H. Voldman 210 $aChichester, West Sussex, England ;$aHoboken, NJ $cJohn Wiley$dc2007 215 $a1 online resource (474 p.) 300 $aDescription based upon print version of record. 311 $a0-470-01642-6 320 $aIncludes bibliographical references and index. 327 $aLatchup; Contents; About the Author; Preface; Acknowledgements; 1 CMOS Latchup; 1.1 CMOS LATCHUP; 1.1.1 CMOS Latchup-What is Latchup?; 1.1.2 CMOS Latchup-Why is Latchup Still an Issue ?; 1.1.3 Early CMOS Latchup History; 1.2 FUNDAMENTAL CONCEPTS OF LATCHUP DESIGN PRACTICE; 1.3 BUILDING A CMOS LATCHUP STRATEGY; 1.3.1 Building a CMOS Business Strategy - 18 Steps in Building a CMOS Latchup Business Strategy; 1.3.2 Building a CMOS Latchup Technology Strategy - 18 Steps in Building a CMOS Latchup Technology Strategy; 1.4 CMOS LATCHUP TECHNOLOGY MIGRATION STRATEGY 327 $a1.5 KEY METRICS OF LATCHUP DESIGN PRACTICE1.6 CMOS LATCHUP TECHNOLOGY TRENDS AND SCALING; 1.7 KEY DEVELOPMENTS; 1.7.1 Key Innovations; 1.7.2 Key Contributions; 1.7.3 Key Patents; 1.8 LATCHUP FAILURE MECHANISMS; 1.9 CMOS LATCHUP EVENTS; 1.9.1 Power-Up Sequence Initiated Latchup; 1.9.2 Input Pin Overshoot and Power-Up Sequence Initiated Latchup; 1.9.3 Input Pin Undershoot and Power-Up Sequence Initiated Latchup; 1.9.4 Multiple Power Supply Power-Up Sequence Initiated Latchup; 1.9.5 Power Supply Overshoot Initiated Latchup; 1.9.6 Power Supply Undershoot Initiated Latchup 327 $a1.9.7 Power Supply (Ground Rail) Undershoot Initiated Latchup1.10 ELECTROSTATIC DISCHARGE SOURCES; 1.10.1 Human Body Model ESD Event; 1.10.2 Machine Model ESD Event; 1.10.3 Cable Discharge Event Source; 1.11 SINGLE EVENT LATCHUP; 1.11.1 High-Energy Photon Emissions; 1.11.2 Alpha Particle Ionizing Source; 1.11.3 Cosmic Ray Source; 1.11.4 Heavy Ion Source; 1.12 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 Bipolar Transistors; 2.1 THE BIPOLAR TRANSISTOR AND CMOS LATCHUP; 2.1.1 Fundamental Equations of Semiconductors and the Drift-Diffusion Current Constitutive Relationships 327 $a2.1.2 Diode Forward Bias Conditions2.1.3 Diode Forward Bias Conditions and High-level Injection; 2.2 BIPOLAR TRANSISTOR; 2.2.1 Bipolar Current Gain; 2.2.2 Bipolar Collector-to-Emitter Transport Factor; 2.2.3 Bipolar Current Characteristics; 2.2.4 Bipolar Model Gummel Plot; 2.2.5 Bipolar Current Model-Ebers-Moll Model; 2.2.6 Bipolar Transistor Base Defect; 2.2.7 Bipolar Transistor Emitter Defect; 2.2.8 Bipolar Base Current - Base Defect and Emitter Defect Relation to Bipolar Current Gain; 2.3 RECOMBINATION MECHANISMS; 2.3.1 Shockley-Read-Hall (SRH) Generation-Recombination Model 327 $a2.3.2 Auger Recombination Model2.3.3 Surface Recombination Mechanisms; 2.3.4 Surface Recombination Velocity; 2.3.5 Recombination Mechanisms and Neutron Irradiation; 2.3.6 Recombination Mechanisms and Gold Recombination Centers; 2.4 PHOTON CURRENTS IN METALLURGICAL JUNCTIONS; 2.5 AVALANCHE BREAKDOWN; 2.5.1 Bipolar Transistor Breakdown; 2.5.2 MOSFET Avalanche Breakdown; 2.6 VERTICAL BIPOLAR TRANSISTOR MODEL; 2.7 LATERAL BIPOLAR TRANSISTOR MODELS; 2.7.1 Lindmayer-Schneider Model; 2.7.2 Bipolar Current Gain with Lateral and Vertical Contributions 327 $a2.7.3 Lateral Bipolar Transistor Models - Nonfield-Assisted 330 $aInterest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand. This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cabl 606 $aMetal oxide semiconductors, Complementary$xDefects 606 $aMetal oxide semiconductors, Complementary$xReliability 615 0$aMetal oxide semiconductors, Complementary$xDefects. 615 0$aMetal oxide semiconductors, Complementary$xReliability. 676 $a621.3815/2 700 $aVoldman$b Steven H$0872423 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910876805703321 996 $aLatchup$94195059 997 $aUNINA