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101 0 $aeng
181   $ctxt
182   $cc
183   $acr
200 10$aInnovative architecture for future generation high-performance processors and systems : 18-19 January, 2001, Maui, Hawaii
210 31$a[Place of publication not identified]$cIEEE Computer Society$d2000
300   $aBibliographic Level Mode of Issuance: Monograph
311 08$a9780769513096 
311 08$a0769513093 
606   $aComputer architecture$vCongresses
606   $aHigh performance computing$vCongresses
606   $aHigh performance processors$vCongresses
606   $aEngineering & Applied Sciences$2HILCC
606   $aComputer Science$2HILCC
615  0$aComputer architecture
615  0$aHigh performance computing
615  0$aHigh performance processors
615  7$aEngineering & Applied Sciences
615  7$aComputer Science
702   $aVeidenbaum$b Alex
702   $aJoe$b Kazuki
712 02$aDARPA/ITO PAC/C Program.
712 02$aMaui High-Performance Computing Center.
712 12$aInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
801  0$bPQKB
906   $aPROCEEDING
912   $a9910872833003321
996   $aInnovative architecture for future generation high-performance processors and systems : 18-19 January, 2001, Maui, Hawaii$92349284
997   $aUNINA