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100   $a20160829d1998      uy 
101 0 $aeng
135   $aur|||||||||||
181   $ctxt
182   $cc
183   $acr
200 10$aMultiple-Valued Logic: ISMVL '98
210 31$a[Place of publication not identified]$cI E E E Imprint$d1998
215   $a1 online resource
300   $aBibliographic Level Mode of Issuance: Monograph
311 08$a9780818683718 
311 08$a0818683716 
327   $aProceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138) -- Table of contents -- Advanced circuit technology to realize post giga-bit DRAM -- Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits -- Ultrafast ternary quantizer using resonant tunneling devices -- A Josephson ternary memory circuit -- A note on realizing multiple-valued logic functions using Akers' cells-cell sizes and path lengths -- Minimization of exclusive sums of multi-valued complex terms for logic cell arrays -- Minimal test set generation for fault diagnosis in R-valued PLAs.
606   $aMany-valued logic$vCongresses
606   $aSwitching theory$vCongresses
615  0$aMany-valued logic
615  0$aSwitching theory
676   $a511.3
801  0$bPQKB
906   $aPROCEEDING
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996   $aMultiple-Valued Logic: ISMVL '98$92326846
997   $aUNINA