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100   $a20160829d2001      uy 
101 0 $aeng
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181   $ctxt
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183   $acr
200 00$a19th IEEE VLSI Test Symposium, 2001, Marina Del Rey, CA
210 31$a[Place of publication not identified]$cIEEE Computer Society Press$d2001
215   $a1 online resource (456 pages)
300   $aBibliographic Level Mode of Issuance: Monograph
311   $a0-7695-1122-8 
330   $aCollects 58 papers from the April/May 2001 symposium that explore new approaches in the testing of electronic circuits and systems. Key areas in testing are discussed, such as BIST, analog measurement, fault tolerance, diagnosis methods, scan chain design, memory test and diagnosis, and test data compression and compaction. Also on the program are sessions on emerging areas that are gaining prominence, including low power testing, testing high speed circuits on low cost testers, processor based self test techniques, and core- based system-on-chip testing. Some of the topics are robust and low cost BIST architectures for sequential fault testing in datapath multipliers, a method for measuring the cycle-to-cycle period jitter of high-frequency clock signals, fault equivalence identification using redundancy information and static and dynamic extraction, and test scheduling for minimal energy consumption under power constraints. No subject index. c. Book News Inc.
606   $aIntegrated circuits$xVery large scale integration$vCongresses
615  0$aIntegrated circuits$xVery large scale integration
676   $a621.395
801  0$bPQKB
906   $aPROCEEDING
912   $a9910872615803321
996   $a19th IEEE VLSI Test Symposium, 2001, Marina Del Rey, CA$92324886
997   $aUNINA