LEADER 01379oam 2200409zu 450 001 9910872613803321 005 20241212215031.0 035 $a(CKB)111026746746524 035 $a(SSID)ssj0000558941 035 $a(PQKBManifestationID)12161304 035 $a(PQKBTitleCode)TC0000558941 035 $a(PQKBWorkID)10581580 035 $a(PQKB)10900854 035 $a(NjHacI)99111026746746524 035 $a(EXLCZ)99111026746746524 100 $a20160829d1998 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$aVerilog HDL Conference and VHDL International Users Forum (IVC/VIUF, `98), 1998 IEEE International 210 31$a[Place of publication not identified]$cI E E E Imprint$d1998 215 $a1 online resource (200 pages) 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9780818684159 311 08$a0818684151 606 $aElectronic circuit design$xData processing$vCongresses 606 $aVHDL (Computer hardware description language) 615 0$aElectronic circuit design$xData processing 615 0$aVHDL (Computer hardware description language) 676 $a621.38150285 801 0$bPQKB 906 $aPROCEEDING 912 $a9910872613803321 996 $aVerilog HDL Conference and VHDL International Users Forum (IVC$92326845 997 $aUNINA