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101 0 $aeng
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181   $ctxt
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183   $acr
200 10$a17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002)
210 31$a[Place of publication not identified]$cIEEE Computer Society Press$d2002
215   $a1 online resource (456 pages)
300   $aBibliographic Level Mode of Issuance: Monograph
311 08$a9780769518312 
311 08$a0769518311 
330   $aThese 45 papers from the November 2002 symposium discuss techniques to assess and enhance the yield, reliability, and availability of VLSI systems. Several of the contributors present new approaches to fault simulation and injection, concurrent error detection, yield prediction, and sequential circuit design for testability. Specific topics include a simplified gate-level fault model for crosstalk effects analysis, input ordering in concurrent checkers to reduce power consumption, on-chip jitter measurement for phase locked loops, and a method to evaluate the repairability of embedded multiple regions DRAMs. No subject index. Annotation copyrighted by Book News, Inc., Portland, OR.
606   $aIntegrated circuits$xVery large scale integration$vCongresses
615  0$aIntegrated circuits$xVery large scale integration
676   $a621.395
801  0$bPQKB
906   $aPROCEEDING
912   $a9910872447003321
996   $a17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002)$92372315
997   $aUNINA