LEADER 01906oam  2200505zu 450 
001 9910872422603321
005 20210807003237.0
035   $a(CKB)111026746701432
035   $a(SSID)ssj0000395442
035   $a(PQKBManifestationID)12118419
035   $a(PQKBTitleCode)TC0000395442
035   $a(PQKBWorkID)10450597
035   $a(PQKB)11460745
035   $a(EXLCZ)99111026746701432
100   $a20160829d2000      uy 
101 0 $aeng
181   $ctxt
182   $cc
183   $acr
200 10$aRecords of the 2000 IEEE International Workshop on Memory Technology, Design and Testing : August 7-8, 2000, San Jose, California
210 31$a[Place of publication not identified]$cIEEE Computer Society$d2000
300   $aBibliographic Level Mode of Issuance: Monograph
311   $a0-7695-0689-5 
606   $aSemiconductor storage devices$xTesting$vCongresses
606   $aRandom access memory$vCongresses
606   $aElectrical & Computer Engineering$2HILCC
606   $aEngineering & Applied Sciences$2HILCC
606   $aElectrical Engineering$2HILCC
615  0$aSemiconductor storage devices$xTesting
615  0$aRandom access memory
615  7$aElectrical & Computer Engineering
615  7$aEngineering & Applied Sciences
615  7$aElectrical Engineering
676   $a621.39/732
702   $aRajsuman$b Rochit
702   $aWik$b T
712 02$aIEEE Computer Society Technical Committee on VLSI,
712 02$aIEEE Computer Society Technical Council on Test Technology.
712 02$aIEEE Computer Society
712 12$aIEEE International Workshop on Memory Technology, Design and Testing
801  0$bPQKB
906   $aPROCEEDING
912   $a9910872422603321
996   $aRecords of the 2000 IEEE International Workshop on Memory Technology, Design and Testing : August 7-8, 2000, San Jose, California$92353609
997   $aUNINA