LEADER 02041oam 2200397zu 450 001 9910872408003321 005 20241212214826.0 035 $a(CKB)111026746702582 035 $a(SSID)ssj0000454762 035 $a(PQKBManifestationID)12158131 035 $a(PQKBTitleCode)TC0000454762 035 $a(PQKBWorkID)10398915 035 $a(PQKB)11381829 035 $a(NjHacI)99111026746702582 035 $a(EXLCZ)99111026746702582 100 $a20160829d2001 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$a2000 International Symposium on Parallel Architecture, Algorithms and Networks (I-SPAN 2000) 210 31$a[Place of publication not identified]$cIEEE Computer Society Press$d2001 215 $a1 online resource (400 pages) 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9780769509365 311 08$a0769509363 330 $aContains 40 papers from the December 2000 symposium that focuses on the design, use, analysis, and application of parallel architectures, algorithms, and networks. The main subjects are routing, fault tolerance, scheduling, ad-hoc networks, and broadcasting. Some of the topics are a parallel tabu search and its hybridization with genetic algorithms, reconfigurable mesh-connected processor arrays using row-column bypassing and direct replacement, three-dimensional embedding of binary trees, optimal one-to-many disjoint paths in folded hypercubes, wavelength assignments in WDM rings with splitable lightpaths, and performance metrics for IP multicast routing. No subject index. Annotation copyrighted by Book News, Inc., Portland, OR. 606 $aParallel processing (Electronic computers)$vCongresses 615 0$aParallel processing (Electronic computers) 676 $a004.35 801 0$bPQKB 906 $aPROCEEDING 912 $a9910872408003321 996 $a2000 International Symposium on Parallel Architecture, Algorithms and Networks (I-SPAN 2000)$92356675 997 $aUNINA