LEADER 02369nam 22003613 450 001 9910865259303321 005 20240614080242.0 010 $a9783031586538$b(electronic bk.) 010 $z9783031586521 035 $a(MiAaPQ)EBC31471650 035 $a(Au-PeEL)EBL31471650 035 $a(CKB)32274020100041 035 $a(EXLCZ)9932274020100041 100 $a20240614d2024 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aASIC Design Implementation Process $eA Complete Framework 205 $a1st ed. 210 1$aCham :$cSpringer,$d2024. 210 4$d©2024. 215 $a1 online resource (143 pages) 311 08$aPrint version: Golshan, Khosrow ASIC Design Implementation Process Cham : Springer,c2024 9783031586521 327 $aIntro -- Foreword -- Trademarks -- Preface -- Acknowledgments -- Disclaimer -- Contents -- About the Author -- Chapter 1: Design Requirements -- 1.1 Specifications -- 1.2 Architecture -- 1.3 Initial Design -- 1.4 Summary -- References -- Chapter 2: Design Validation -- 2.1 FPGA Design -- 2.2 FPGA Programming -- 2.3 Reference Board Design -- 2.4 Hardware and Software Validation -- 2.5 Summary -- References -- Chapter 3: Design Synthesis -- 3.1 Timing Constraints -- 3.2 Optimization Constraints -- 3.3 Design Rule Constraints -- 3.4 Summary -- References -- Chapter 4: Physical Design -- 4.1 Floorplanning -- 4.2 Placement -- 4.3 Clock Tree Synthesis -- 4.4 Routing -- 4.5 Summary -- References -- Chapter 5: Design Verification -- 5.1 Functional Verification -- 5.2 Timing Verification -- 5.3 Physical Verification -- 5.4 Summary -- References -- Chapter 6: ASIC Testing -- 6.1 Functional Test -- 6.2 Scan Test -- 6.3 Boundary Scan Test -- 6.4 Fault Detection -- 6.5 Parametric Test -- 6.6 Current and Very Low-Level Voltage Test -- 6.7 Built-In-Self-Test -- 6.8 Parallel Module Test -- 6.9 System Test -- 6.10 Summary -- References -- Chapter 7: ASIC Qualification -- 7.1 Electro-Static Discharge Test -- 7.2 Latch-up Test -- 7.3 Wafer Acceptance Test -- 7.4 Summary -- References -- Index. 700 $aGolshan$b Khosrow$0867018 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 912 $a9910865259303321 996 $aASIC Design Implementation Process$94169310 997 $aUNINA