LEADER 01056nam2-22003251i-450- 001 990000345470403321 005 20001010 035 $a000034547 035 $aFED01000034547 035 $a(Aleph)000034547FED01 035 $a000034547 100 $a20001010d--------km-y0itay50------ba 101 0 $aita 105 $ay-------001yy 200 1 $aWahrscheinlichkeitsrechnung (Ars conjectandi)$fVon Jakob Bernoulli. Erster und zweiter theil. Uebersetzt undherausgegeben von R. Haussner. 210 $aLeipzig$cVerlag von Engelmann$d1899 215 $a162 p., 19 cm 225 1 $aOstwalds Klassiker der exakten Wissenschaften$vNr. 107 461 0$1001000034542$12001$aUeber Physikalische Kraftlinien 676 $a030 700 1$aBernoulli,$bJakob$f<1654-1705>$019629 702 1$aHaussner,$bRobert 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990000345470403321 952 $a04 210-1/107$bCI$fDINCH 959 $aDINCH 996 $aWahrscheinlichkeitsrechnung (Ars conjectandi$9124810 997 $aUNINA DB $aING01 LEADER 00828nam0-2200289---450- 001 990008309320403321 005 20060407111444.0 035 $a000830932 035 $aFED01000830932 035 $a(Aleph)000830932FED01 035 $a000830932 100 $a20060407d1954----km-y0itay50------ba 101 0 $ager 102 $aDE 105 $ay-------001yy 200 1 $a<>Kaiser in der Spätantiche$fWilhelm Ensslin 210 $aMünchen$cOldenbourg$d1954 215 $ap. 449-468 300 $aEstratto da: Historische Zeitschrift, 177 (1954) 700 1$aEnsslin,$bWilhelm$f<1885-1965>$0180005 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990008309320403321 952 $aDirez. E-017$bs.i. ddr$fDDR$m21-9863 959 $aDDR 996 $aKaiser in der Spätantiche$9745700 997 $aUNINA LEADER 00838nam0 2200265 450 001 9910302960503321 005 20190114095330.0 010 $a978-88-921-1372-5 100 $a20190114d2018----km y0itay50 ba 101 0 $aita 102 $aIT 105 $ay 001yy 200 1 $aAd normam iuris$eparadigmi della legalità nel diritto canonico$fBeatrice Serra$gprefazione di Gaetano Lo Castro 210 $aTorino$cGiappichelli$d2018 215 $aXXIII, 298 p.$d23 cm 225 1 $aCollana di studi di diritto canonico ed ecclesiastico$iSezione canonistica$v45 700 1$aSerra,$bBeatrice$0194165 702 1$aLo Castro,$bGaetano 801 0$aIT$bUNINA$gREICAT$2UNIMARC 901 $aBK 912 $a9910302960503321 952 $aIII EE 133$bE95$fDCEC 959 $aDCEC 996 $aAd normam iuris$91541813 997 $aUNINA LEADER 06204nam 2200469 450 001 9910830781803321 005 20230629215417.0 010 $a1-119-78272-4 010 $a1-119-78271-6 010 $a1-119-78273-2 035 $a(CKB)4100000011974750 035 $a(MiAaPQ)EBC6647274 035 $a(Au-PeEL)EBL6647274 035 $a(OCoLC)1263873213 035 $a(EXLCZ)994100000011974750 100 $a20220317d2021 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cn$2rdamedia 183 $anc$2rdacarrier 200 10$aDigital system design using FSMs $ea practical learning approach /$fPeter D. Minns 210 1$aHoboken, NJ :$cJohn Wiley & Sons, Inc.,$d2021. 215 $a1 online resource (340 pages) 311 $a1-119-78270-8 327 $aCover -- Title Page -- Copyright Page -- Contents -- Preface -- Acknowledgements -- About the Companion Website -- Guide to Supplementary Resources -- Chapter 1 Introduction to Finite State Machines -- 1.1 Some Notes on Style -- Chapter 2 Using FSMs to Control External Devices -- 2.1 Introduction -- Chapter 3 Introduction to FSM Synthesis -- 3.1 Introduction -- 3.2 Tutorials Covering Chapters 1, 2, and 3 -- 3.2.1 Binary data serial transmitter FSM -- 3.2.2 The high low FSM system -- 3.2.3 The clocked watchdog timer FSM -- 3.2.4 The asynchronous receiver system clocked FSM -- Chapter 4 Asynchronous FSM Methods -- 4.1 Introduction to Asynchronous FSM -- 4.2 Summary -- 4.3 Tutorials -- 4.3.1 FSM motor with fault detection -- 4.3.2 The mower in four and two states -- Chapter 5 Clocked One Hot Method of FSM Design -- 5.1 Introduction -- 5.2 Tutorials on the Clocked one Hot FSM Method -- 5.2.1 Seven-state system clocked one hot method -- 5.2.2 Memory tester FSM -- 5.2.3 Eight-bit sequence detector FSM -- Chapter 6 Further Event-Driven FSM Design -- 6.1 Introduction -- 6.2 Conclusions -- Chapter 7 Petri Net FSM Design -- 7.1 Introduction -- 7.2 Tutorials Using Petri Net FSM -- 7.2.1 Controlled shared resource Petri nets -- 7.2.2 Serial clock-driven Petri net FSM -- 7.2.3 Using asynchronous (event-driven) design with Petri nets -- 7.3 Conclusions -- Appendix A1: Boolean Algebra -- A1.1 Basic Gate Symbols -- A1.2 The Exclusive OR and Exclusive NOR -- A1.3 Laws of Boolean Algebra -- A1.3.1 Basic OR rules -- A1.3.2 Basic AND rules -- A1.3.3 Associative and commutative laws -- A1.3.4 Distributive laws -- A1.3.5 Auxiliary rule for static 1 hazard removal -- A1.3.6 Consensus theorem -- A1.3.7 The effect of signal delay in logic gates -- A1.3.8 De-Morgan's theorem -- A1.4 Examples of Applying the Laws of Boolean Algebra -- A1.4.1 Converting AND-OR to NAND. 327 $aA1.4.2 Converting AND-OR to NOR -- A1.4.3 Logical adjacency rule -- A1.5 Summary -- Appendix A2: Use of Verilog HDL and Logisim to FSM -- A2.1 The Single-Pulse Generator with Memory Clock-Driven FSM -- A2.2 Test Bench Module and its Purpose -- A2.3 Using Synapticad Software -- A2.4 More Direct Method -- A2.5 A Very Simple Guide to Using the Logisim Simulator -- A2.5.1 The Logisim top level menu items -- A2.6 Using Flip-Flops in a Circuit -- A2.7 Example Single-Pulse FSM -- A2.8 How to Use the Simulator to Simulate the Single-Pulse FSM -- A2.8.1 Using Logisim with the truth table approach -- A2.9 Using Logisim with the Truth Table Approach -- A2.9.1 Useful note -- A2.10 Summary -- Appendix A3: Counters, Shift Registers, Input, and Output with an FSM -- A3.1 Basic Down Synchronous Binary Counter Development -- A3.2 Example of a Four-Bit Synchronous Up Counter with T Type Flip-Flops -- A3.3 Parallel Loading Counters - Using T Flip-Flops -- A3.4 Using D Flip-Flops To Build Parallel Loading Counters -- A3.5 Simple Binary Up Counter with Parallel Inputs -- A3.6 Clock Circuit to Drive the Counter (and FSM) -- A3.7 Counter Design Using Don't Care States -- A3.8 Shift Registers -- A3.9 Dealing with Input and Output Signals Using FSM -- A3.10 Using Logisim to Work with Larger FSM Systems -- A3.10.1 The equations -- A3.11 Summary -- Appendix A3: Counters, Shift Registers, Input, and Output with an FSM -- A4.1 Introduction -- A4.2 The Single-Pulse/Multiple-Pulse Generator with Memory FSM -- A4.3 The Memory Tester FSM Revisited -- A4.4 Summary -- Appendix A5: Programming a Finite State Machine -- A5.1 Introduction -- A5.2 The Parallel Loading Counter -- A5.3 The Multiplexer -- A5.4 The Micro Instruction -- A5.5 The Memory -- A5.6 The Instruction Set -- A5.7 Simple Example: Single-Pulse FSM -- A5.8 The Final Example. 327 $aA5.9 The Program Code -- A5.10 Returning Unused States Via Other Transition Paths -- A5.11 Summary -- Appendix A6: The Rotational Detector Using Logisim Simulator with Sub-Circuits -- A6.1 Using the Two-State Diagram Arrangement -- Bibliography -- Index -- EULA. 330 $a"A finite state machine (FSM) is a computation model that can be implemented with hardware or software and can be used to simulate sequential logic and some computer programs. Finite state machines can be used to model problems in many fields including mathematics, artificial intelligence, games, and linguistics. This is a complete update of the author's earlier book, FSM-Based Digital Design using Verilog HDL (Wiley 2008). Whilst the essential foundation content remains, the book has been considerably refreshed to cover the design of Finite State Machines (FSM) in place of Microprocessors, using a novel form of State Machines based on Toggle Flip Flops (TFF) and Data Flip Flops (DFF). It follows a Linear Programmed Learning approach, enabling the reader to learn at their own pace, and to design their own FSM based systems."--$cProvided by publisher. 606 $aDigital electronics 606 $aSequential machine theory 615 0$aDigital electronics. 615 0$aSequential machine theory. 676 $a621.381 700 $aMinns$b Peter D.$0995482 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910830781803321 996 $aDigital system design using FSMs$94067784 997 $aUNINA