LEADER 05537nam 2200673Ia 450 001 9910829969203321 005 20230704011926.0 010 $a1-283-86967-5 010 $a3-527-62306-X 010 $a3-527-62305-1 035 $a(CKB)1000000000687934 035 $a(EBL)700875 035 $a(SSID)ssj0000388248 035 $a(PQKBManifestationID)11250451 035 $a(PQKBTitleCode)TC0000388248 035 $a(PQKBWorkID)10411155 035 $a(PQKB)10835800 035 $a(MiAaPQ)EBC700875 035 $a(OCoLC)299046802 035 $a(EXLCZ)991000000000687934 100 $a20071212d2008 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 00$aHandbook of 3D integration$b[electronic resource] $etechnology and applications of 3D integrated circuits /$fedited by Philip Garrou, Christopher Bower and Peter Ramm 210 $aWeinheim $cWiley-VCH$d2008 215 $a1 online resource (801 p.) 300 $aDescription based upon print version of record. 311 $a3-527-32034-2 320 $aIncludes bibliographical references and index. 327 $aHandbook of 3D Integration; Contents; Preface; List of Contributors; 1 Introduction to 3D Integration; 1.1 Introduction; 1.2 Historical Evolution of Stacked Wafer Concepts; 1.3 3D Packaging vs 3D Integration; 1.4 Non-TSV 3D Stacking Technologies; 1.4.1 Irvine Sensors; 1.4.2 UTCS (Ultrathin Chip Stacking) IMEC, CNRS, U. Barcelona; 1.4.3 Fujitsu; 1.4.4 Fraunhofer/IZM; 1.4.5 3D Plus/Leti; 1.4.6 Toshiba System Block Module; References; 2 Drivers for 3D Integration; 2.1 Introduction; 2.2 Electrical Performance; 2.2.1 Signal Seed; 2.2.2 Memory Latency; 2.3 Power Consumption and Noise; 2.3.1 Noise 327 $a2.4 Form Factor2.4.1 Non-Volatile Memory Technology: Flash; 2.4.2 Volatile Memory Technology: SRAM and DRAM; 2.4.3 CMOS Image Sensors; 2.5 Lower Cost; 2.6 Application Based Drivers; 2.6.1 Microprocessors; 2.6.2 Memory; 2.6.3 Sensors; 2.6.4 Fields Programmable Gate Arrays (FPGAs); References; 3 Overview of 3D Integration Process Technology; 3.1 3D Integration Terminology; 3.1.1 Through Silicon Vias (TSVs); 3.1.2 Wafer Thinning; 3.1.3 Aligned Wafer/IC Bonding; 3.2 Processing Sequences; 3.3 Technologies for 3D Integration; 3.3.1 TSV Formation; 3.3.2 Temporary Bonding to Carrier Wafer 327 $a3.3.3 Thinning3.3.4 Alignment/Bonding; References; I Through Silicon Via Fabrication; 4 Deep Reactive Ion Etching of Through Silicon Vias; 4.1 Introduction; 4.1.1 Deep Reactive Ion Etching as Breakthrough Enabling Through-Wafer Interconnects; 4.1.2 State of the Art and Basic Principles in DRIE; 4.1.3 Bosch Process; 4.1.4 Alternatives for Via Hole Creation; 4.2 DRIE Equipment and Characterization; 4.2.1 High-Density Plasma Reactors; 4.2.2 Plasma Chemistry; 4.2.3 Plasma Diagnostics and Surface Analysis; 4.3 DRIE Processing; 4.3.1 Mask Issues; 4.3.2 High Aspect Ratio Features 327 $a4.3.3 Sidewall Passivation, Depassivation and Profile Control4.4 Practical Solutions in Via Etching; 4.4.1 Undercut and Scallop Reduction; 4.4.2 Sidewall Roughness Minimization; 4.4.3 Loading Effects; 4.4.4 Notching at Dielectric Interfaces; 4.4.5 Inspection of Via Structures; 4.4.6 In Situ Trench Depth Measurement; 4.5 Concluding Remarks; Appendix A: Glossary of Abbreviations; Appendix B: Examples of DRIE Recipes; References; 5 Laser Ablation; 5.1 Introduction; 5.2 Laser Technology for 3D Packaging; 5.2.1 Advantages; 5.2.2 Disadvantages; 5.3 For Si Substrate; 5.3.1 Difficulties 327 $a5.3.2 Results5.4 Results for 3D Chip Stacking; 5.5 Reliabilities; 5.6 The Future; References; 6 SiO(2); 6.1 Introduction; 6.2 Dielectric CVD; 6.2.1 Sub-Atmospheric CVD; 6.2.2 Process Sequence of O(3)-Activated SACVD Deposition; 6.2.3 Conformal SACVD O(3) TEOS Films for 3D Integration; 6.3 Dielectric Film Properties; 6.4 3D-Specifics Regarding SiO(2) Dielectrics; 6.4.1 Wafer Pre-Processing; 6.4.2 Backside Processing Requirements on SiO(2) Film Conformality in TSVs; 6.4.3 SiO(2) Film Deposition on Thinned Silicon Substrates; 6.5 Concluding Remarks; References; 7 Insulation - Organic Dielectrics 327 $a7.1 Parylene 330 $aThe first encompassing treatise of this new, but very important field puts the known physical limitations for classic 2D electronics into perspective with the requirements for further electronics developments and market necessities. This two-volume handbook presents 3D solutions to the feature density problem, addressing all important issues, such as wafer processing, die bonding, packaging technology, and thermal aspects.It begins with an introductory part, which defines necessary goals, existing issues and relates 3D integration to the semiconductor roadmap of the industry. Before going 606 $aIntegrated circuits 606 $aIntegrated circuits$xDesign and construction 606 $aSemiconductor wafers 606 $aThree-dimensional imaging 615 0$aIntegrated circuits. 615 0$aIntegrated circuits$xDesign and construction. 615 0$aSemiconductor wafers. 615 0$aThree-dimensional imaging. 676 $a621.381 676 $a621.3815 701 $aGarrou$b Philip E$01615373 701 $aBower$b Christopher Andrew$01615374 701 $aRamm$b Peter$01615375 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910829969203321 996 $aHandbook of 3D integration$93945536 997 $aUNINA