LEADER 01087nam0-2200337---450- 001 990010002520403321 005 20151006125343.0 035 $a001000252 035 $aFED01001000252 035 $a(Aleph)001000252FED01 035 $a001000252 100 $a20151001d2014----km-y0itay50------ba 101 0 $aita 102 $aIT 105 $aa-------001yy 200 1 $aStorie locali nell'Abruzzo di età moderna$e1504-1806$fCristina Ciccarelli$gpresentazione di Irene Fosi 210 $aL'Aquila$cLibreria Colacchi$d©2014 215 $a380 p.$cill.$d24 cm 225 1 $aBibliografica$fDeputazione abruzzese di storia patria$v12 300 $aSul front. Deputazione Abruzzese di Storia Patria 610 0 $aAbruzzo$aStoria$a1504-1806$aBibliografia 610 0 $aAbruzzo$aStoria$a1504-1806$aFonti archivistiche 676 $a945.71$v22$zita 700 1$aCiccarelli,$bCristina 702 1$aFosi,$bIrene 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990010002520403321 952 $a945.71 CIC 1$bBIBL.2015/501$fFLFBC 959 $aFLFBC 997 $aUNINA LEADER 05817nam 22008293u 450 001 9910826714103321 005 20210107031200.0 010 $a9786613157355 010 $a9781283157353 010 $a1283157357 010 $a9781118009918 010 $a1118009916 010 $a9781118009925 010 $a1118009924 010 $a9781118009901 010 $a1118009908 035 $a(CKB)2550000000039100 035 $a(EBL)693260 035 $a(SSID)ssj0000521630 035 $a(PQKBManifestationID)11913727 035 $a(PQKBTitleCode)TC0000521630 035 $a(PQKBWorkID)10523722 035 $a(PQKB)11574996 035 $a(OCoLC)746326310 035 $a(CaSebORM)9780470643365 035 $a(MiAaPQ)EBC693260 035 $a(Perlego)1014342 035 $a(EXLCZ)992550000000039100 100 $a20131014d2011|||| u|| | 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aComputer System Design $eSystem-on-Chip 205 $a1st edition 210 $aHoboken $cWiley$d2011 215 $a1 online resource (356 p.) 300 $aDescription based upon print version of record. 311 08$a9780470643365 311 08$a0470643366 320 $aIncludes bibliographical references (p. 316-328) and index. 327 $aCOMPUTER SYSTEM DESIGN; CONTENTS; PREFACE; LIST OF ABBREVIATIONS AND ACRONYMS; 1: Introduction to the Systems Approach; 1.1 SYSTEM ARCHITECTURE: AN OVERVIEW; 1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS; 1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE; 1.4 PROCESSOR ARCHITECTURES; 1.4.1 Processor: A Functional View; 1.4.2 Processor: An Architectural View; 1.5 MEMORY AND ADDRESSING; 1.5.1 SOC Memory Examples; 1.5.2 Addressing: The Architecture of Memory; 1.5.3 Memory for SOC Operating System; 1.6 SYSTEM-LEVEL INTERCONNECTION; 1.6.1 Bus-Based Approach 327 $a1.6.2 Network-on-Chip Approach1.7 AN APPROACH FOR SOC DESIGN; 1.7.1 Requirements and Specifications; 1.7.2 Design Iteration; 1.8 SYSTEM ARCHITECTURE AND COMPLEXITY; 1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC; 1.9.1 Factors Affecting Product Costs; 1.9.2 Modeling Product Economics and Technology Complexity: The Lesson for SOC; 1.10 DEALING WITH DESIGN COMPLEXITY; 1.10.1 Buying IP; 1.10.2 Reconfiguration; 1.11 CONCLUSIONS; 1.12 PROBLEM SET; 2: Chip Basics: Time, Area, Power, Reliability, and Configurability; 2.1 INTRODUCTION; 2.1.1 Design Trade-Offs; 2.1.2 Requirements and Specifications 327 $a2.2 CYCLE TIME2.2.1 Defining a Cycle; 2.2.2 Optimum Pipeline; 2.2.3 Performance; 2.3 DIE AREA AND COST; 2.3.1 Processor Area; 2.3.2 Processor Subunits; 2.4 IDEAL AND PRACTICAL SCALING; 2.5 POWER; 2.6 AREA-TIME-POWER TRADE-OFFS IN PROCESSOR DESIGN; 2.6.1 Workstation Processor; 2.6.2 Embedded Processor; 2.7 RELIABILITY; 2.7.1 Dealing with Physical Faults; 2.7.2 Error Detection and Correction; 2.7.3 Dealing with Manufacturing Faults; 2.7.4 Memory and Function Scrubbing; 2.8 CONFIGURABILITY; 2.8.1 Why Reconfigurable Design?; 2.8.2 Area Estimate of Reconfigurable Devices; 2.9 CONCLUSION 327 $a2.10 PROBLEM SET3: Processors; 3.1 INTRODUCTION; 3.2 PROCESSOR SELECTION FOR SOC; 3.2.1 Overview; 3.2.2 Example: Soft Processors; 3.2.3 Examples: Processor Core Selection; 3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE; 3.3.1 Instruction Set; 3.3.2 Some Instruction Set Conventions; 3.3.3 Branches; 3.3.4 Interrupts and Exceptions; 3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE; 3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING; 3.5.1 The Instruction Decoder and Interlocks; 3.5.2 Bypassing; 3.5.3 Execution Unit; 3.6 BUFFERS: MINIMIZING PIPELINE DELAYS; 3.6.1 Mean Request Rate Buffers 327 $a3.6.2 Buffers Designed for a Fixed or Maximum Request Rate3.7 BRANCHES: REDUCING THE COST OF BRANCHES; 3.7.1 Branch Target Capture: Branch Target Buffers (BTBs); 3.7.2 Branch Prediction; 3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR; 3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS; 3.9.1 Vector Functional Units; 3.10 VLIW PROCESSORS; 3.11 SUPERSCALAR PROCESSORS; 3.11.1 Data Dependencies; 3.11.2 Detecting Instruction Concurrency; 3.11.3 A Simple Implementation; 3.11.4 Preserving State with Out-of-Order Execution 327 $a3.12 PROCESSOR EVOLUTION AND TWO EXAMPLES 330 $aThe next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses th 517 3 $aSystem-on-chip 606 $aSystems on a chip 606 $aSystems on a chip 606 $aSystems on a chip 606 $aElectrical & Computer Engineering$2HILCC 606 $aEngineering & Applied Sciences$2HILCC 606 $aElectrical Engineering$2HILCC 615 4$aSystems on a chip. 615 4$aSystems on a chip. 615 0$aSystems on a chip. 615 7$aElectrical & Computer Engineering 615 7$aEngineering & Applied Sciences 615 7$aElectrical Engineering 676 $a004.1 700 $aFlynn$b Michael J$0727526 701 $aLuk$b Wayne$01682625 801 0$bAU-PeEL 801 1$bAU-PeEL 801 2$bAU-PeEL 906 $aBOOK 912 $a9910826714103321 996 $aComputer System Design$94052888 997 $aUNINA