LEADER 05466nam 2200673 n 450 001 9910825105903321 005 20200520144314.0 010 $a1-281-00979-2 010 $a9786611009793 010 $a0-08-047709-7 035 $a(CKB)1000000000349961 035 $a(EBL)234967 035 $a(OCoLC)213331960 035 $a(SSID)ssj0000136751 035 $a(PQKBManifestationID)11144300 035 $a(PQKBTitleCode)TC0000136751 035 $a(PQKBWorkID)10084014 035 $a(PQKB)11292172 035 $a(MiAaPQ)EBC234967 035 $a(Au-PeEL)EBL234967 035 $a(CaPaEBR)ebr10127899 035 $a(CaONFJC)MIL100979 035 $a(OCoLC)936903375 035 $a(EXLCZ)991000000000349961 100 $a20050817d2005 fy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aDemystifying chipmaking /$fby Richard F. Yanda, Michael Heynes and Anne K. Miller 205 $a1st ed. 210 $aOxford $cNewnes ;$aAmsterdam $cElsevier$d2005 215 $a1 online resource (276 p.) 300 $aDescription based upon print version of record. 311 $a0-7506-7760-0 320 $aIncludes bibliographical references and index. 327 $aCover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding 327 $a4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout 327 $aSection 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition 327 $aSection 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 327 $a2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization 327 $aSection 4: Photo/Etch for Contact Holes 330 $aThis book takes the reader through the actual manufacturing process of making a typical chip, from start to finish, including a detailed discussion of each step, in plain language. The evolution of today's technology is added to the story, as seen through the eyes of the engineers who solved some of the problems. The authors are well suited to that discussion since they are three of those same engineers. They have a broad exposure to the industry and its technology that extends all the way back to Shockley Laboratories, the first semiconductor manufacturer in Silicon Valley.The CMOS (C 606 $aLogic circuits$xDesign and construction 606 $aMetal oxide semiconductors, Complementary 615 0$aLogic circuits$xDesign and construction. 615 0$aMetal oxide semiconductors, Complementary. 676 $a621.39732 700 $aYanda$b Richard F$01624514 701 $aHeynes$b Michael$01624515 701 $aMiller$b Anne K$0125426 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910825105903321 996 $aDemystifying chipmaking$93959522 997 $aUNINA