LEADER 02181oam 2200481 450 001 9910483488103321 005 20210417082247.0 010 $a3-030-58782-7 024 7 $a10.1007/978-3-030-58782-6 035 $a(CKB)4100000011558836 035 $a(DE-He213)978-3-030-58782-6 035 $a(MiAaPQ)EBC6384520 035 $a(PPN)252504275 035 $a(EXLCZ)994100000011558836 100 $a20210417d2021 uy 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 00$aUse of cassava wastewater and scheelite residues in ceramic formulations /$fWilson Acchar, Vamberto Monteiro da Silva, editors 205 $a1st ed. 2021. 210 1$aCham, Switzerland :$cSpringer,$d[2021] 210 4$d©2021 215 $a1 online resource (V, 116 p. 49 illus., 15 illus. in color.) 225 1 $aGreen energy and technology 311 $a3-030-58781-9 320 $aIncludes bibliographical references. 327 $aCassava Wastewater: An Introduction, Characterization and Potential -- Soil-Cement Brick with Cassava Wastewater -- Ecological brick of mineral residues and cassava wastewater -- Mortar produced with scheelite residue and cassava wastewater -- Earthbag construction system with cassava wastewater. 330 $aThis book presents original results on the use of cassava wastewater as a substitute for potable water in ceramic formulations. It evaluates the physical and mechanical properties as well as the microstructure of the materials produced, comparing the products obtained from the incorporating effluent with the conventional materials used in the construction industry. 410 0$aGreen energy and technology. 606 $aAgricultural wastes$xRecycling 615 0$aAgricultural wastes$xRecycling. 676 $a628.746 702 $aAcchar$b Wilson 702 $aMonteiro da Silva$b Vamberto 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bUtOrBLW 906 $aBOOK 912 $a9910483488103321 996 $aUse of cassava wastewater and scheelite residues in ceramic formulations$92843882 997 $aUNINA LEADER 06029nam 2200745 a 450 001 9910819603603321 005 20240313065055.0 010 $a9781118468654 010 $a1118468651 010 $a9781283735643 010 $a1283735644 010 $a9781118468616 010 $a1118468619 035 $a(CKB)2670000000271084 035 $a(EBL)1051822 035 $a(SSID)ssj0000754622 035 $a(PQKBManifestationID)11489344 035 $a(PQKBTitleCode)TC0000754622 035 $a(PQKBWorkID)10716684 035 $a(PQKB)10638504 035 $a(DLC) 2012042415 035 $a(Au-PeEL)EBL1051822 035 $a(CaPaEBR)ebr10618832 035 $a(CaONFJC)MIL404814 035 $a(CaSebORM)9781118468647 035 $a(MiAaPQ)EBC1051822 035 $a(OCoLC)813301166 035 $a(PPN)166822566 035 $a(Perlego)1001913 035 $a(EXLCZ)992670000000271084 100 $a20121016d2013 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 00$aEmbedded systems $ehardware, design, and implementation /$fedited by Krzysztof Iniewski 205 $a1st ed. 210 $aHoboken, N.J. $cJohn Wiley & Sons, Inc.$d2013 215 $a1 online resource (387 p.) 300 $aDescription based upon print version of record. 311 08$a9781118468647 311 08$a1118468643 311 08$a9781118352151 311 08$a1118352157 320 $aIncludes bibliographical references and index. 327 $aTitle page; Copyright page; Contents; Preface; Contributors; 1: Low Power Multicore Processors for Embedded Systems; 1.1 Multicore Chip with Highly Efficient Cores; 1.2 SuperHTM RISC Engine Family (SH) Processor Cores; 1.2.1 History of SH Processor Cores; 1.2.2 Highly Efficient ISA; 1.2.3 Asymmetric In-Order Dual-Issue Superscalar Architecture; 1.3 SH-X: A Highly Efficient CPU Core; 1.3.1 Microarchitecture Selections; 1.3.2 Improved Superpipeline Structure; 1.3.3 Branch Prediction and Out-of-Order Branch Issue; 1.3.4 Low Power Technologies; 1.3.5 Performance and Efficiency Evaluations 327 $a1.4 SH-X FPU: A Highly Efficient FPU1.4.1 FPU Architecture of SH Processors; 1.4.2 Implementation of SH-X FPU; 1.4.3 Performance Evaluations with 3D Graphics Benchmark; 1.5 SH-X2: Frequency and Efficiency Enhanced Core; 1.5.1 Frequency Enhancement; 1.5.2 Low Power Technologies; 1.6 SH-X3: Multicore Architecture Extension; 1.6.1 SH-X3 Core Specifications; 1.6.2 Symmetric and Asymmetric Multiprocessor Support; 1.6.3 Core Snoop Sequence Optimization; 1.6.4 Dynamic Power Management; 1.6.5 RP-1 Prototype Chip; 1.6.6 RP-2 Prototype Chip; 1.7 SH-X4: ISA and Address Space Extension 327 $a1.7.1 SH-X4 Core Specifications1.7.2 Efficient ISA Extension; 1.7.3 Address Space Extension; 1.7.4 Data Transfer Unit; 1.7.5 RP-X Prototype Chip; References; 2: Special-Purpose Hardware for Computational Biology; 2.1 Molecular Dynamics Simulations on Graphics Processing Units; 2.1.1 Molecular Mechanics Force Fields; 2.1.2 Graphics Processing Units for MD Simulations; 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations; 2.2.1 High-Throughput Interaction Subsystem; 2.2.2 Hardware Description of the Flexible Subsystem; 2.2.3 Performance and Conclusions 327 $a2.3 Quantum MC Applications on Field-Programmable Gate Arrays2.3.1 Energy Computation and WF Kernels; 2.3.2 Hardware Architecture; 2.3.3 PE and WF Computation Kernels; 2.4 Conclusions and Future Directions; References; 3: Embedded GPU Design; 3.1 Introduction; 3.2 System Architecture; 3.3 Graphics Modules Design; 3.3.1 RISC Processor; 3.3.2 Geometry Processor; 3.3.3 Rendering Engine; 3.4 System Power Management; 3.4.1 Multiple Power-Domain Management; 3.4.2 Power Management Unit; 3.5 Implementation Results; 3.5.1 Chip Implementation; 3.5.2 Comparisons; 3.6 Conclusion; References 327 $a4: Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors4.1 Introduction; 4.2 The DVP Interface; 4.3 The iBRIDGE-BB Architecture; 4.3.1 Configuring the iBRIDGE-BB; 4.3.2 Operation of the iBRIDGE-BB; 4.3.3 Description of Internal Blocks; 4.4 Hardware Implementation; 4.4.1 Verification in Field-Programmable Gate Array; 4.4.2 Application in Image Compression; 4.4.3 Application-Specific Integrated Circuit (ASIC) Synthesis and Performance Analysis; 4.5 Conclusion; Acknowledgments; References; 5: Embedded Computing Systems on FPGAs; 5.1 FPGA Architecture 327 $a5.2 FPGA Configuration Technology 330 $a"The book begins with an introduction of embedded computing systems, honing in on system on a chip (SoCs), multi-processor System-on-Chip (MPSoCs) and Network operation centers (NoCs). It covers on-chip integration of software and custom hardware accelerators, as well as fabric flexibility, custom architectures, and the multiple I/O standards that facilitate PCB integration. The second portion of the book focuses on the technologies associated with embedded computing systems. It also covers the basics of field-programmable gate array (FPGA), digital signal processing (DSP) and application-specific integrated circuit (ASIC) technology, architectural support for on-chip integration of custom accelerators with processors and O/S support for these systems. The third area focuses on architecture, testability and computer-aided design (CAD) support for embedded systems, soft processors, heterogeneous resources, on-chip storage. The final section covers software support, in particular O/S (linux, research and technology organization (RTO))"--$cProvided by publisher. 606 $aEmbedded computer systems 615 0$aEmbedded computer systems. 676 $a006.2/2 686 $aTEC008070$2bisacsh 701 $aIniewski$b Krzysztof$0845507 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910819603603321 996 $aEmbedded systems$93917152 997 $aUNINA