LEADER 05647nam 2200721 a 450 001 9910818619503321 005 20200520144314.0 010 $a1-281-09615-6 010 $a9786611096151 010 $a0-08-055601-9 035 $a(CKB)1000000000402924 035 $a(EBL)328310 035 $a(OCoLC)437196962 035 $a(SSID)ssj0000077627 035 $a(PQKBManifestationID)11107507 035 $a(PQKBTitleCode)TC0000077627 035 $a(PQKBWorkID)10060268 035 $a(PQKB)10259975 035 $a(Au-PeEL)EBL328310 035 $a(CaPaEBR)ebr10204252 035 $a(CaONFJC)MIL109615 035 $a(CaSebORM)9780123705228 035 $a(MiAaPQ)EBC328310 035 $a(OCoLC)434042365 035 $a(OCoLC)ocn434042365 035 $a(EXLCZ)991000000000402924 100 $a20070718d2008 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 00$aReconfigurable computing $ethe theory and practice of FPGA-based computation /$fedited by Scott Hauck and Andre? DeHon 205 $a1st edition 210 $aAmsterdam ;$aBoston $cMorgan Kaufmann$dc2008 215 $a1 online resource (945 p.) 225 1 $aThe Morgan Kaufmann series in systems on silicon 300 $aDescription based upon print version of record. 311 $a0-12-370522-3 320 $aIncludes bibliographical references and index. 327 $aFront Cover; Reconfigurable Computing; Copyright Page; Table of Contents; List of Contributors; Preface; Introduction; Part I: Reconfigurable Computing Hardware; Chapter 1. Device Architecture; 1.1 Logic-The Computational Fabric; 1.2 The Array and Interconnect; 1.3 Extending Logic; 1.4 Configuration; 1.5 Case Studies; 1.6 Summary; References; Chapter 2. Reconfigurable Computing Architectures; 2.1 Reconfigurable Processing Fabric Architectures; 2.2 RPF Integration into Traditional Computing Systems; 2.3 Summary and Future Work; References; Chapter 3. Reconfigurable Computing Systems 327 $a3.1 Early Systems3.2 PAM, VCC, and Splash; 3.3 Small-Scale Reconfigurable Systems; 3.4 Circuit Emulation; 3.5 Accelerating Technology; 3.6 Reconfigurable Supercomputing; 3.7 Non-FPGA Research; 3.8 Other System Issues; 3.9 The Future of Reconfigurable Systems; References; Chapter 4. Reconfiguration Management; 4.1 Reconfiguration; 4.2 Configuration Architectures; 4.3 Managing the Reconfiguration Process; 4.4 Reducing Configuration Transfer Time; 4.5 Configuration Security; 4.6 Summary; References; Part II: Programming Reconfigurable Systems; Chapter 5. Compute Models and System Architectures 327 $a5.1 Compute Models5.2 System Architectures; References; Chapter 6. Programming FPGA Applications in VHDL; 6.1 VHDL Programming; 6.2 Hardware Compilation Flow; 6.3 Limitations of VHDL; References; Chapter 7. Compiling C for Spatial Computing; 7.1 Overview of How C Code Runs on Spatial Hardware; 7.2 Automatic Compilation; 7.3 Uses and Variations of C Compilation to Hardware; 7.4 Summary; References; Chapter 8. Programming Streaming FPGA Applications Using Block Diagrams in Simulink; 8.1 Designing High-Performance Datapaths Using Stream-Based Operators; 8.2 An Image-Processing Design Driver 327 $a8.3 Specifying Control in Simulink8.4 Component Reuse: Libraries of Simple and Complex Subsystems; 8.5 Summary; References; Chapter 9. Stream Computations Organized for Reconfigurable Execution; 9.1 Programming; 9.2 System Architecture and Execution Patterns; 9.3 Compilation; 9.4 Runtime; 9.5 Highlights; References; Chapter 10. Programming Data Parallel FPGA Applications Using the SIMD/Vector Model; 10.1 SIMD Computing on FPGAs: An Example; 10.2 SIMD Processing Architectures; 10.3 Data Parallel Languages; 10.4 Reconfigurable Computers for SIMD/Vector Processing 327 $a10.5 Variations of SIMD/Vector Computing10.6 Pipelined SIMD/Vector Processing; 10.7 Summary; References; Chapter 11. Operating System Support for Reconfigurable Computing; 11.1 History; 11.2 Abstracted Hardware Resources; 11.3 Flexible Binding; 11.4 Scheduling; 11.5 Communication; 11.6 Synchronization; 11.7 Protection; 11.8 Summary; References; Chapter 12. The JHDL Design and Debug System; 12.1 JHDL Background and Motivation; 12.2 The JHDL Design Language; 12.3 The JHDL CAD System; 12.4 JHDL'S Hardware Mode; 12.5 Advanced JHDL Capabilities; 12.6 Summary; References 327 $aPart III: Mapping Designs to Reconfigurable Platforms 330 $aReconfigurable Computing marks a revolutionary and hot topic that bridges the gap between the separate worlds of hardware and software design- the key feature of reconfigurable computing is its groundbreaking ability to perform computations in hardware to increase performance while retaining the flexibility of a software solution. Reconfigurable computers serve as affordable, fast, and accurate tools for developing designs ranging from single chip architectures to multi-chip and embedded systems. Scott Hauck and Andre DeHon have assembled a group of the key experts in the fields 410 0$aMorgan Kaufmann series in systems on silicon. 606 $aAdaptive computing systems 606 $aField programmable gate arrays 615 0$aAdaptive computing systems. 615 0$aField programmable gate arrays. 676 $a621.39/5 676 $a621.395 701 $aHauck$b Scott$0867834 701 $aDeHon$b Andre?$01677379 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910818619503321 996 $aReconfigurable computing$94044212 997 $aUNINA