LEADER 01953nam 2200589 450 001 9910817445603321 005 20230803222142.0 010 $a1-58948-395-2 035 $a(CKB)2550000001346100 035 $a(MiAaPQ)EBC3238266 035 $a(Au-PeEL)EBL3238266 035 $a(CaPaEBR)ebr10931725 035 $a(CaONFJC)MIL638972 035 $a(OCoLC)892699669 035 $a(EXLCZ)992550000001346100 100 $a20140924h20142014 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $2rdacontent 182 $2rdamedia 183 $2rdacarrier 200 10$aModernizing American land records $eorder upon chaos /$fEarl F. Epstein and Bernard J. Niemann Jr 210 1$aRedlands, California :$cESRI Press,$d2014. 210 4$dİ2014 215 $a1 online resource (218 pages) 311 $a1-58948-304-9 311 $a1-322-07721-5 320 $aIncludes bibliographical references and index. 606 $aLand use$zUnited States$xHistory 606 $aLand use$zUnited States$xData processing 606 $aLand tenure$xGovernment policy$zUnited States 606 $aLand use$xInformation services 606 $aLand tenure$zUnited States 606 $aInformation storage and retrieval systems$xLand use$zUnited States 606 $aGeographic information systems$zUnited States 615 0$aLand use$xHistory. 615 0$aLand use$xData processing. 615 0$aLand tenure$xGovernment policy 615 0$aLand use$xInformation services. 615 0$aLand tenure 615 0$aInformation storage and retrieval systems$xLand use 615 0$aGeographic information systems 676 $a025.06/33330973 700 $aEpstein$b Earl F.$01695910 702 $aNiemann$b Bernard J. 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910817445603321 996 $aModernizing American land records$94075473 997 $aUNINA LEADER 02097oam 2200433zu 450 001 9910140891803321 005 20241212220020.0 010 $a9780769542768 010 $a076954276X 035 $a(CKB)2670000000058819 035 $a(SSID)ssj0000527485 035 $a(PQKBManifestationID)12162396 035 $a(PQKBTitleCode)TC0000527485 035 $a(PQKBWorkID)10525668 035 $a(PQKB)10060804 035 $a(NjHacI)992670000000058819 035 $a(EXLCZ)992670000000058819 100 $a20160829d2010 uy 101 0 $aeng 135 $aur||||||||||| 181 $ctxt 182 $cc 183 $acr 200 10$a2010 22nd International Symposium on Computer Architecture and High Performance Computing Workshops 210 31$a[Place of publication not identified]$cIEEE$d2010 215 $a1 online resource 300 $aBibliographic Level Mode of Issuance: Monograph 311 08$a9781424488773 311 08$a142448877X 330 $aMulticore architectures are an important contribution in computing technology since they are capable of providing more processing power with better cost-benefit than single-core processors. Cores execute instructions independently but share critical resources such as L2 cache memory and data channels. Clusters using multicore architectures or multiprocessors chips (MPC's) suggest a hierarchical memory environment. Parallel applications should take advantage of such memory hierarchy to achieve high performance. This paper presents a performance analysis of a synthetic application in a multicore cluster and introduces a preliminary architecture model that considers communication through both shared memory and data channels and its impact on the application performance. 606 $aComputer architecture$vCongresses 615 0$aComputer architecture 676 $a004.22 702 $aieee 801 0$bPQKB 906 $aPROCEEDING 912 $a9910140891803321 996 $a2010 22nd International Symposium on Computer Architecture and High Performance Computing Workshops$92423988 997 $aUNINA