LEADER 03518nam 2200601 450 001 9910815413303321 005 20200520144314.0 010 $a0-12-800979-9 010 $a0-12-801178-5 035 $a(CKB)2670000000585799 035 $a(CaPaEBR)ebrary10996814 035 $a(SSID)ssj0001453738 035 $a(PQKBManifestationID)11894540 035 $a(PQKBTitleCode)TC0001453738 035 $a(PQKBWorkID)11492229 035 $a(PQKB)10663909 035 $a(Au-PeEL)EBL1888542 035 $a(CaPaEBR)ebr10996814 035 $a(CaONFJC)MIL678997 035 $a(OCoLC)894609116 035 $a(CaSebORM)9780128009796 035 $a(MiAaPQ)EBC1888542 035 $a(PPN)194309428 035 $a(EXLCZ)992670000000585799 100 $a20150106h20152015 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt 182 $cc 183 $acr 200 00$aNetworks-on-chip $efrom implementations to programming paradigms /$fSheng Ma [and three others] ; editor-in-chief Zhiying Wang 205 $aFirst edition. 210 1$aWaltham, Massachusetts :$cMorgan Kaufmann,$d2015. 210 4$dİ2015 215 $a1 online resource (383 p.) 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a1-322-47715-9 320 $aIncludes bibliographical references and index. 330 $aNetworks-on-Chip: From Implementations to Programming Paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC and high-level programming paradigms. This textbook is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture and Networks-on-Chip. It is also intended for practitioners in the industry in the area of microprocessor design, especially the many-core processor design with a network-on-chip. Graduates can learn many practical and theoretical lessons from this course, and also can be motivated to delve further into the ideas and designs proposed in this book. Industrial engineers can refer to this book to make practical tradeoffs as well. Graduates and engineers who focus on off-chip network design can also refer to this book to achieve deadlock-free routing algorithm designs. Provides thorough and insightful exploration of NoC design space. Description from low-level logic implementations to co-optimizations of high-level program paradigms and NoCs. The coherent and uniform format offers readers a clear, quick and efficient exploration of NoC design space Covers many novel and exciting research ideas, which encourage researchers to further delve into these topics. Presents both engineering and theoretical contributions. The detailed description of the router, buffer and topology implementations, comparisons and analysis are of high engineering value. 606 $aNetworks on a chip$xDesign and construction 606 $aNetworks on a chip$xReliability 615 0$aNetworks on a chip$xDesign and construction. 615 0$aNetworks on a chip$xReliability. 676 $a621.381531 702 $aMa$b Sheng 702 $aWang$b Zhiying 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910815413303321 996 $aNetworks-on-chip$94033902 997 $aUNINA