LEADER 01368nam 2200349 n 450 001 996394527803316 005 20200824121902.0 035 $a(CKB)4940000000120752 035 $a(EEBO)2240936067 035 $a(UnM)99834614e 035 $a(UnM)99834614 035 $a(EXLCZ)994940000000120752 100 $a19970507d1698 uy | 101 0 $aeng 135 $aurbn||||a|bb| 200 12$aA new abstract of the mine-adventure: or, an undertaking, advantagious for the publick good, charitable to the poor, and profitable to every person who shall be concern'd therein$b[electronic resource] 210 $a[London? $cs.n.$d1698] 215 $a1 sheet ([2] p.) 300 $aAttributed to Humphrey Mackworth by Wing. 300 $aImprint from Wing. 300 $aReproduction of the original at the British Library. 330 $aeebo-0018 606 $aMines and mineral resources$zWales$vEarly works to 1800 615 0$aMines and mineral resources 700 $aMackworth$b Humphrey$cSir,$f1657-1727.$01010752 801 0$bCu-RivES 801 1$bCu-RivES 801 2$bWaOLN 906 $aBOOK 912 $a996394527803316 996 $aA new abstract of the mine-adventure: or, an undertaking, advantagious for the publick good, charitable to the poor, and profitable to every person who shall be concern'd therein$92350401 997 $aUNISA LEADER 03449nam 2200565 450 001 9910814730503321 005 20230120012954.0 010 $a0-12-802145-4 010 $a0-12-802370-8 035 $a(CKB)2670000000585899 035 $a(CaPaEBR)ebrary10999972 035 $a(SSID)ssj0001454827 035 $a(PQKBManifestationID)11864146 035 $a(PQKBTitleCode)TC0001454827 035 $a(PQKBWorkID)11498262 035 $a(PQKB)10221892 035 $a(Au-PeEL)EBL1888751 035 $a(CaPaEBR)ebr10999972 035 $a(CaONFJC)MIL679360 035 $a(OCoLC)898326670 035 $a(CaSebORM)9780128021453 035 $a(MiAaPQ)EBC1888751 035 $a(EXLCZ)992670000000585899 100 $a20150110h20152015 uy 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt 182 $cc 183 $acr 200 10$aBuilding an intelligence-led security program /$fAllan Liska ; Tim Gallo, technical editor 205 $aFirst edition. 210 1$aWaltham, Massachusetts :$cSyngress,$d2015. 210 4$dİ2015 215 $a1 online resource (192 p.) 300 $aBibliographic Level Mode of Issuance: Monograph 311 $a1-322-48078-8 320 $aIncludes bibliographical references at the end of each chapters and index. 330 $aAs recently as five years ago, securing a network meant putting in a firewall, intrusion detection system, and installing antivirus software on the desktop. Unfortunately, attackers have grown more nimble and effective, meaning that traditional security programs are no longer effective. Today's effective cyber security programs take these best practices and overlay them with intelligence. Adding cyber threat intelligence can help security teams uncover events not detected by traditional security platforms and correlate seemingly disparate events across the network. Properly-implemented intelligence also makes the life of the security practitioner easier by helping him more effectively prioritize and respond to security incidents. The problem with current efforts is that many security practitioners don't know how to properly implement an intelligence-led program, or are afraid that it is out of their budget. Building an Intelligence-Led Security Program is the first book to show how to implement an intelligence-led program in your enterprise on any budget. It will show you how to implement a security information a security information and event management system, collect and analyze logs, and how to practice real cyber threat intelligence. You'll learn how to understand your network in-depth so that you can protect it in the best possible way. Provides a roadmap and direction on how to build an intelligence-led information security program to protect your company. Learn how to understand your network through logs and client monitoring, so you can effectively evaluate threat intelligence. Learn how to use popular tools such as BIND, SNORT, squid, STIX, TAXII, CyBox, and splunk to conduct network intelligence. 606 $aComputer networks$xSecurity measures 615 0$aComputer networks$xSecurity measures. 676 $a658.478 700 $aLiska$b Allan$0943565 702 $aGallo$b Tim 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910814730503321 996 $aBuilding an intelligence-led security program$93945262 997 $aUNINA LEADER 05914nam 22007454a 450 001 9911019333403321 005 20200520144314.0 010 $a9786610654390 010 $a9781280654398 010 $a1280654392 010 $a9780470041956 010 $a0470041951 010 $a9780470041949 010 $a0470041943 035 $a(CKB)1000000000354739 035 $a(EBL)275873 035 $a(SSID)ssj0000101330 035 $a(PQKBManifestationID)11109136 035 $a(PQKBTitleCode)TC0000101330 035 $a(PQKBWorkID)10060143 035 $a(PQKB)10395232 035 $a(MiAaPQ)EBC275873 035 $a(OCoLC)777633356 035 $a(CaSebORM)9780471772552 035 $a(OCoLC)840104834 035 $a(OCoLC)ocn840104834 035 $a(Perlego)2750475 035 $a(EXLCZ)991000000000354739 100 $a20060105d2006 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aAll-digital frequency synthesizer in deep-submicron CMOS /$fRobert Bogdan Staszewski, Poras T. Balasara 205 $a1st edition 210 $aHoboken, N.J. $cWiley-Interscience$dc2006 215 $a1 online resource (281 p.) 300 $aDescription based upon print version of record. 311 08$a9780471772552 311 08$a0471772550 320 $aIncludes bibliographical references (p. 247-252) and index. 327 $aALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS; CONTENTS; PREFACE; Acknowledgments; 1 INTRODUCTION; 1.1 Frequency Synthesis; 1.1.1 Noise in Oscillators; 1.1.2 Frequency Synthesis Techniques; 1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver; 1.2.1 Transmitter; 1.2.2 Receiver; 1.2.3 Toward Direct Transmitter Modulation; 1.3 Frequency Synthesizers for Mobile Communications; 1.3.1 Integer-N PLL Architecture; 1.3.2 Fractional-N PLL Architecture; 1.3.3 Toward an All-Digital PLL Approach; 1.4 Implementation of an RF Synthesizer 327 $a1.4.1 CMOS vs. Traditional RF Process Technologies1.4.2 Deep-Submicron CMOS; 1.4.3 Digitally Intensive Approach; 1.4.4 System Integration; 1.4.5 System Integration Challenges for Deep-Submicron CMOS; 2 DIGITALLY CONTROLLED OSCILLATOR; 2.1 Varactor in a Deep-Submicron CMOS Process; 2.2 Fully Digital Control of Oscillating Frequency; 2.3 LC Tank; 2.4 Oscillator Core; 2.5 Open-Loop Narrowband Digital-to-Frequency Conversion; 2.6 Example Implementation; 2.7 Time-Domain Mathematical Model of a DCO; 2.8 Summary; 3 NORMALIZED DCO; 3.1 Oscillator Transfer Function and Gain; 3.2 DCO Gain Estimation 327 $a3.3 DCO Gain Normalization3.4 Principle of Synchronously Optimal DCO Tuning Word Retiming; 3.5 Time Dithering of DCO Tuning Input; 3.5.1 Oscillator Tune Time Dithering Principle; 3.5.2 Direct Time Dithering of Tuning Input; 3.5.3 Update Clock Dithering Scheme; 3.6 Implementation of PVT and Acquisition DCO Bits; 3.7 Implementation of Tracking DCO Bits; 3.7.1 High-Speed Dithering of Fractional Varactors; 3.7.2 Dynamic Element Matching of Varactors; 3.7.3 DCO Varactor Rearrangement; 3.8 Time-Domain Model; 3.9 Summary; 4 ALL-DIGITAL PHASE-LOCKED LOOP; 4.1 Phase-Domain Operation 327 $a4.2 Reference Clock Retiming4.3 Phase Detection; 4.3.1 Difference Mode of ADPLL Operation; 4.3.2 Integer-Domain Operation; 4.4 Modulo Arithmetic of the Reference and Variable Phases; 4.4.1 Variable-Phase Accumulator (PV Block); 4.5 Time-to-Digital Converter; 4.5.1 Frequency Reference Edge Estimation; 4.6 Fractional Error Estimator; 4.6.1 Fractional-Division Ratio Compensation; 4.6.2 TDC Resolution Effect on Estimated Frequency Resolution; 4.6.3 Active Removal of Fractional Spurs Through TDC (Optional); 4.7 Frequency Reference Retiming by a DCO Clock; 4.7.1 Sense Amplifier-Based Flip-Flop 327 $a4.7.2 General Idea of Clock Retiming4.7.3 Implementation; 4.7.4 Time-Deferred Calculation of the Variable Phase (Optional); 4.8 Loop Gain Factor; 4.8.1 Phase-Error Dynamic Range; 4.9 Phase-Domain ADPLL Architecture; 4.9.1 Close-in Spurs Due to Injection Pulling; 4.10 PLL Frequency Response; 4.10.1 Conversion Between the s- and z-Domains; 4.11 Noise and Error Sources; 4.11.1 TDC Resolution Effect on Phase Noise; 4.11.2 Phase Noise Due to DCO ?? Dithering; 4.12 Type II ADPLL; 4.12.1 PLL Frequency Response of a Type II Loop; 4.13 Higher-Order ADPLL; 4.13.1 PLL Stability Analysis 327 $a4.14 Nonlinear Differential Term of an ADPLL 330 $aA new and innovative paradigm for RF frequency synthesis and wireless transmitter design Learn the techniques for designing and implementing an all-digital RF frequency synthesizer. In contrast to traditional RF techniques, this innovative book sets forth digitally intensive design techniques that lead the way to the development of low-cost, low-power, and highly integrated circuits for RF functions in deep submicron CMOS processes. Furthermore, the authors demonstrate how the architecture enables readers to integrate an RF front-end with the digital back-end onto a single silicon die 606 $aFrequency synthesizers$xDesign and construction 606 $aWireless communication systems$xEquipment and supplies$xDesign and construction 606 $aMetal oxide semiconductors, Complementary$xDesign and construction 615 0$aFrequency synthesizers$xDesign and construction. 615 0$aWireless communication systems$xEquipment and supplies$xDesign and construction. 615 0$aMetal oxide semiconductors, Complementary$xDesign and construction. 676 $a621.3815/486 700 $aStaszewski$b Robert Bogdan$f1965-$0302249 701 $aBalsara$b Poras T.$f1961-$0302250 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9911019333403321 996 $aAll-digital frequency synthesizer in deep-submicron CMOS$9730932 997 $aUNINA