LEADER 05589nam 22006974a 450 001 9910808929603321 005 20200520144314.0 010 $a1-280-96685-8 010 $a9786610966851 010 $a0-08-047245-1 035 $a(CKB)1000000000364065 035 $a(EBL)288758 035 $a(OCoLC)476041894 035 $a(SSID)ssj0000074508 035 $a(PQKBManifestationID)11110242 035 $a(PQKBTitleCode)TC0000074508 035 $a(PQKBWorkID)10127239 035 $a(PQKB)10092393 035 $a(Au-PeEL)EBL288758 035 $a(CaPaEBR)ebr10169773 035 $a(CaONFJC)MIL96685 035 $a(CaSebORM)9780123724984 035 $a(MiAaPQ)EBC288758 035 $a(OCoLC)435501526 035 $a(OCoLC)ocn435501526 035 $a(EXLCZ)991000000000364065 100 $a20060406d2006 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aDesigning SOCs with configured cores $eunleashing the Tensilica Xtensa and diamond cores /$fSteve Leibson 205 $a1st edition 210 $aAmsterdam ;$aBoston $cMorgan Kaufmann Publishers$dc2006 215 $a1 online resource (341 p.) 225 1 $aThe Morgan Kaufmann series in systems on silicon 300 $aDescription based upon print version of record. 311 $a0-12-372498-8 320 $aIncludes bibliographical references and index. 327 $aFront Cover; About the Author; Title page; Copyright Page; Table of contents; Foreword; Preface; Acknowledgements; 1 Introduction to 21st-Century SOC Design; 1.1 The Start of Something Big; 1.2 Few Pins = Massive Multiplexing; 1.3 Third Time's a Charm; 1.4 The Microprocessor: A Universal System Building Block; 1.5 The Consequences of Performance-in the Macro World; 1.6 Increasing Processor Performance in the Micro World; 1.7 I/O Bandwidth and Processor Core Clock Rate; 1.8 Multitasking and Processor Core Clock Rate; 1.9 System-Design Evolution 327 $a1.10 Heterogeneous- and Homogeneous-Processor System-Design Approaches1.11 The Rise of MPSOC Design; 1.12 Veering Away from Processor Multitasking in SOC Design; 1.13 Processors: The Original, Reusable Design Block; 1.14 A Closer Look at 21st-Century Processor Cores for SOC Design; Bibliography; 2 The SOC Design Flow; 2.1 System-Design Goals; 2.2 The ASIC Design Flow; 2.3 The ad-hoc SOC Design Flow; 2.4 A Systematic MPSOC Design Flow; 2.5 Computational Alternatives; 2.6 Communication Alternatives; 2.7 Cycle-Accurate System Simulation; 2.8 Detailed Implementation 327 $a2.9 Summary: Handling SOC ComplexityBibliography; 3 Xtensa Architectural Basics; 3.1 Introduction to Configurable Processor Architectures; 3.2 Xtensa Registers; 3.3 Register Windowing; 3.4 The Xtensa Program Counter; 3.5 Memory Address Space; 3.6 Bit and Byte Ordering; 3.7 Base Xtensa Instructions; 3.8 Benchmarking the Xtensa Core ISA; Bibliography; 4 Basic Processor Configurability; 4.1 Processor Generation; 4.2 Xtensa Processor Block Diagram; 4.3 Pre-Configured Processor Cores; 4.4 Basics of TIE; 4.5 TIE Instructions; 4.6 Improving Application Performance Using TIE 327 $a4.7 TIE Registers and Register Files4.8 TIE Ports; 4.9 TIE Queue Interfaces; 4.10 Combining Instruction Extensions with Queues; 4.11 Diamond Standard Series Processor Cores-Dealing with Complexity; Bibliography; 5 MPSOC System Architectures and Design Tools; 5.1 SOC Architectural Evolution; 5.2 The Consequences of Architectural Evolution; 5.3 Memory Interfaces; 5.4 Memory Caches; 5.5 Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF; 5.6 The PIF; 5.7 Ports and Queue Interfaces; 5.8 SOC Connection Topologies; 5.9 Shared-Memory Topologies; 5.10 Direct Port-Connected Topologies 327 $a5.11 Queue-Based System Topologies5.12 Existing Design Tools for Complex SOC Designs; 5.13 MPSOC Architectural-Design Tools; 5.14 Platform Design; 5.15 An MPSOC-Design Tool; 5.16 MPSOC System-Level Simulation Example; 5.17 SOC Design in the 21st Century; Bibliography; 6 Introduction to Diamond Standard Series Processor Cores; 6.1 The Diamond Standard Series of 32-bit Processor Cores; 6.2 Diamond Standard Series Software-Development Tools; 6.3 Diamond Standard Series Feature Summary; 6.4 Diamond Standard Series Processor Core Hardware Overview and Comparison 327 $a6.5 Diamond-Core Local-Memory Interfaces 330 $aMicroprocessor cores used for SOC design are the direct descendents of Intel's original 4004 microprocessor. Just as packaged microprocessor ICs vary widely in their attributes, so do microprocessors packaged as IP cores. However, SOC designers still compare and select processor cores the way they previously compared and selected packaged microprocessor ICs. The big problem with this selection method is that it assumes that the laws of the microprocessor universe have remained unchanged for decades. This assumption is no longer valid.Processor cores for SOC designs can be far more plas 410 0$aMorgan Kaufmann series in systems on silicon. 606 $aEmbedded computer systems$xDesign and construction 606 $aSystems on a chip$xDesign and construction 615 0$aEmbedded computer systems$xDesign and construction. 615 0$aSystems on a chip$xDesign and construction. 676 $a621.3815 700 $aLeibson$b Steve$01692035 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910808929603321 996 $aDesigning SOCs with configured cores$94068839 997 $aUNINA