LEADER 05922nam 2200817Ia 450 001 9910808850803321 005 20200520144314.0 010 $a9786613621894 010 $a9781280592065 010 $a1280592060 010 $a9781118273135 010 $a1118273133 010 $a9781118273142 010 $a1118273141 010 $a9781118273111 010 $a1118273117 035 $a(CKB)2670000000159962 035 $a(EBL)843655 035 $a(SSID)ssj0000611797 035 $a(PQKBManifestationID)11355636 035 $a(PQKBTitleCode)TC0000611797 035 $a(PQKBWorkID)10666251 035 $a(PQKB)11763326 035 $a(Au-PeEL)EBL843655 035 $a(CaPaEBR)ebr10538699 035 $a(CaONFJC)MIL362189 035 $a(OCoLC)784124227 035 $a(CaSebORM)9781118243046 035 $a(MiAaPQ)EBC843655 035 $a(OCoLC)810072366 035 $a(OCoLC)ocn810072366 035 $a(Perlego)1003871 035 $a(EXLCZ)992670000000159962 100 $a20111017d2012 uy 0 101 0 $aeng 135 $aurunu||||| 181 $ctxt 182 $cc 183 $acr 200 10$aEngineering the CMOS library $eenhancing digital design kits for competitive silicon /$fDavid Doman 205 $a1st edition 210 $aHoboken, N.J. $cJohn Wiley & Sons$dc2012 215 $a1 online resource (343 p.) 300 $aDescription based upon print version of record. 311 08$a9781118243046 311 08$a1118243048 327 $aEngineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon; Contents; Preface; Acknowledgments; 1: Introduction; 1.1: Adding Project-Specific Functions, Drive Strengths, Views, and Corners; 1.2: What Is a DDK?; 2: Stdcell Libraries; 2.1: Lesson from the Real World: Manager's Perspective and Engineer's Perspective; 2.2: What Is a Stdcell?; 2.2.1: Combinational Functions; 2.2.2: Sequential Functions; 2.2.3: Clock Functions; 2.3: Extended Library Offerings; 2.3.1: Low-Power Support; 2.4: Boutique Library Offerings; 2.5: Concepts for Further Study; 3: IO Libraries 327 $a3.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 3.2: Extension Capable Architectures versus Function Complete Architectures; 3.3: Electrostatic Discharge Considerations; 3.3.1: Footprints; 3.3.2: Custom Design Versus Standard IO Design Comparison; 3.3.3: The Need for Maintaining Multiple IO Footprint Regions on an IC; 3.3.4: Circuit Under Pad; 3.4: Concepts for Further Study; 4: Memory Compilers; 4.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 4.2: Single Ports, Dual Ports, and ROM: The Compiler 327 $a4.3: Nonvolatile Memories: The Block 4.4: Special-Purpose Memories: The Custom; 4.5: Concepts for Further Study; 5: Other Functions; 5.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 5.2: Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs; 5.3: Low-Power Support Structures; 5.4: Stitching Structures; 5.4.1: Core-Fill Cells; 5.4.2: IO-Fill Cells; 5.4.3: DECAP Cells; 5.4.4: CMP-Fill Cells; 5.4.5: Spare Logic Cells; 5.4.6: Probe-Point Cells; 5.4.7: Antenna Diodes; 5.4.8: Test-Debug Diodes; 5.4.9: Others 327 $a5.5: Hard, Firm, and Soft Boxes 5.6: Concepts for Further Study; 6: Physical Views; 6.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 6.2: Picking an Architecture; 6.3: Measuring Density; 6.4: The Need and the Way to Work with Fabrication Houses; 6.5: Concepts for Further Study; 7: SPICE; 7.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 7.2: Why a Tool More Than 40 Years Old Is Still Useful; 7.3: Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye; 7.4: Sufficient Parasitics 327 $a7.5: Concepts for Further Study 8: Timing Views; 8.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 8.2: Performance Limits and Measurement; 8.3: Default Versus Conditional Arcs; 8.4: Break-Point Optimization; 8.5: A Word on Setup and Hold; 8.6: Failure Mechanisms and Roll-Off; 8.7: Supporting Efficient Synthesis; 8.7.1: SPICE, Monotonic Arrays, and Favorite Stdcells; 8.7.2: SPICE, Positive Arrays, and Useful Skew; 8.8: Supporting Efficient Timing Closure; 8.9: Design Corner Specific Timing Views; 8.10: Nonlinear Timing Views are so ""Old Hat"" . . . 327 $a8.11: Concepts for Further Study 330 $aShows readers how to gain the competitive edge in the integrated circuit marketplace This book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard-cell libraries and shows design engineers and managers how to use this knowledge to beat the competition. Engineering the CMOS Library reveals step by step how the generic, foundry-provided standard-cell library is built, and how to extract value from existing std-cells and EDA tools in order to produce tighter-margined, smaller, faster, less power-hungry, and 517 3 $aEnhancing digital design kits for competitive silicon 517 3 $aEngineering the complementary metal-oxide-semiconductor library 606 $aDigital integrated circuits$xDesign and construction 606 $aMetal oxide semiconductors, Complementary 606 $aIndustrial efficiency 615 0$aDigital integrated circuits$xDesign and construction. 615 0$aMetal oxide semiconductors, Complementary. 615 0$aIndustrial efficiency. 676 $a621.3815 686 $aTEC008050$2bisacsh 700 $aDoman$b David$01657010 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910808850803321 996 $aEngineering the CMOS library$94010173 997 $aUNINA