LEADER 01006nam a2200265 i 4500 001 991001583309707536 008 120208s1995 xxk b 001 0 eng d 020 $a9780521474740 035 $ab14037464-39ule_inst 040 $aFacoltà SSPT$bita 082 0 $a809.93 100 1 $aWard, Ian,$d1963-$0241818 245 10$aLaw and literature :$bpossibilities and perspectives /$cIan Ward 260 $aCambridge ;$aNew York :$bCambridge University Press,$cc1995 300 $axi, 264 p. ;$c24 cm 504 $aCon bibliografia (p. 246-260) e indice 650 4$aDiritto nella letteratura$xStoria$ySec. 19.-20. 650 4$aLetteratura$xStoria e critica 650 4$aDiritto e letteratura 907 $a.b14037464$b02-04-14$c08-02-12 912 $a991001583309707536 945 $aLE021 809.93 WAR01.01$g1$i2020000036296$lle021$op$pE29.95$q-$rn$s- $t0$u1$v0$w1$x0$y.i15377829$z08-02-12 996 $aLaw and literature$9244425 997 $aUNISALENTO 998 $ale020$b08-02-12$cm$da $e-$feng$gxxk$h0$i0 LEADER 03799nam 2200733Ia 450 001 9910808037403321 005 20241120173247.0 010 $a9786612382185 010 $a9781282382183 010 $a1282382187 010 $a9780470824092 010 $a0470824093 010 $a9780470824085 010 $a0470824085 024 7 $a10.1002/9780470824092 035 $a(CKB)1000000000799847 035 $a(EBL)479860 035 $a(SSID)ssj0000366925 035 $a(PQKBManifestationID)11275066 035 $a(PQKBTitleCode)TC0000366925 035 $a(PQKBWorkID)10418689 035 $a(PQKB)11324759 035 $a(MiAaPQ)EBC479860 035 $a(CaBNVSL)mat05453758 035 $a(IDAMS)0b00006481237fee 035 $a(IEEE)5453758 035 $a(Au-PeEL)EBL479860 035 $a(CaPaEBR)ebr10325826 035 $a(CaONFJC)MIL238218 035 $a(OCoLC)669008259 035 $a(PPN)254409873 035 $a(Perlego)2786764 035 $a(EXLCZ)991000000000799847 100 $a20081027d2009 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aTransient-induced latchup in CMOS integrated circuits /$fMing-Dou Ker and Sheng-Fu Hsu 205 $a1st ed. 210 $aSingapore ;$aHoboken, NJ $cWiley$dc2009 215 $a1 online resource (265 p.) 300 $aDescription based upon print version of record. 311 08$a9780470824078 311 08$a0470824077 320 $aIncludes bibliographical references and index. 327 $aPhysical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process. 330 $a"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description. 606 $aMetal oxide semiconductors, Complementary$xDefects 606 $aMetal oxide semiconductors, Complementary$xReliability 615 0$aMetal oxide semiconductors, Complementary$xDefects. 615 0$aMetal oxide semiconductors, Complementary$xReliability. 676 $a621.3815 676 $a621.39/5 700 $aKer$b Ming-Dou$01656164 701 $aHsu$b Sheng-Fu$01656165 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910808037403321 996 $aTransient-induced latchup in CMOS integrated circuits$94008872 997 $aUNINA