LEADER 04240nam  22007695  450 
001 9910788468203321
005 20200705111130.0
010   $a1-283-62185-1
010   $a9786613934307
010   $a1-4419-9660-5
024 7 $a10.1007/978-1-4419-9660-2
035   $a(CKB)3190000000023831
035   $a(EBL)994370
035   $a(OCoLC)796934946
035   $a(SSID)ssj0000695331
035   $a(PQKBManifestationID)11399681
035   $a(PQKBTitleCode)TC0000695331
035   $a(PQKBWorkID)10676006
035   $a(PQKB)10612450
035   $a(DE-He213)978-1-4419-9660-2
035   $a(MiAaPQ)EBC994370
035   $a(PPN)168291495
035   $a(EXLCZ)993190000000023831
100   $a20120614d2012      u|             0
101 0 $aeng
135   $aur|n|---|||||
181   $ctxt
182   $cc
183   $acr
200 10$aDSP Architecture Design Essentials$b[electronic resource] /$fby Dejan Markovi?, Robert W. Brodersen
205   $a1st ed. 2012.
210  1$aNew York, NY :$cSpringer US :$cImprint: Springer,$d2012.
215   $a1 online resource (353 p.)
225 1 $aElectrical Engineering Essentials,$x2363-8494
300   $aDescription based upon print version of record.
311   $a1-4419-9659-1 
327   $aEnergy and Delay Models -- Circuit Optimization -- Architectural Techniques -- Architecture Flexibility -- Arithmetic for DSP -- CORDIC, Divider, Square Root -- Digital Filters -- Time-Frequency Analysis -- Data-Flow Graph Model -- Wordlength Optimization -- Architectural Optimization -- Simulink-Hardware Flow -- Multi-GHz Radio DSP -- Dedicated MHz-rate Decoders -- Flexible MHz-rate Decoder -- kHz-rate Neural Processors -- Brief Outlook.
330   $aIn DSP Architecture Design Essentials, authors Dejan Markovi? and Robert W. Brodersen cover a key subject for the successful realization of DSP algorithms for communications, multimedia, and healthcare applications. The book addresses the need for DSP architecture design that maps advanced DSP algorithms to hardware in the most power- and area-efficient way. The key feature of this text is a design methodology based on a high-level design model that leads to hardware implementation with minimum power and area. The methodology includes algorithm-level considerations such as automated word-length reduction and intrinsic data properties that can be leveraged to reduce hardware complexity. From a high-level data-flow graph model, an architecture exploration methodology based on linear programming is used to create an array of architectural solutions tailored to the underlying hardware technology. The book is supplemented with online material: bibliography, design examples, CAD tutorials and custom software.
410  0$aElectrical Engineering Essentials,$x2363-8494
606   $aElectronic circuits
606   $aSignal processing
606   $aImage processing
606   $aSpeech processing systems
606   $aElectrical engineering
606   $aMicroprocessors
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aSignal, Image and Speech Processing$3https://scigraph.springernature.com/ontologies/product-market-codes/T24051
606   $aElectrical Engineering$3https://scigraph.springernature.com/ontologies/product-market-codes/T24000
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
615  0$aElectronic circuits.
615  0$aSignal processing.
615  0$aImage processing.
615  0$aSpeech processing systems.
615  0$aElectrical engineering.
615  0$aMicroprocessors.
615 14$aCircuits and Systems.
615 24$aSignal, Image and Speech Processing.
615 24$aElectrical Engineering.
615 24$aProcessor Architectures.
676   $a621.3815
676   $a621.3822
700   $aMarkovi?$b Dejan$4aut$4http://id.loc.gov/vocabulary/relators/aut$01569270
702   $aBrodersen$b Robert W$4aut$4http://id.loc.gov/vocabulary/relators/aut
906   $aBOOK
912   $a9910788468203321
996   $aDSP Architecture Design Essentials$93842032
997   $aUNINA