LEADER 01490nam--2200421---450- 001 990002401280203316 005 20100104105541.0 010 $a88-387-2573-X 035 $a000240128 035 $aUSA01000240128 035 $a(ALEPH)000240128USA01 035 $a000240128 100 $a20050221d2004----km-y0enga50------ba 101 0 $aita 102 $aIT 105 $ay---z---001yy 200 1 $aCondono, concordato, preventivo$enovita fiscali 2004$eproroga del 41%, i nuovi limiti sulle ristrutturazioni edilizie : tecnotremonti per ricerca e formazione$fGiovanni Fiore, Antonio Claser 210 $aSantarcangelo di Romagna$cMaggioli$dcopyr. 2004 215 $a136 p.$d30 cm$e1 fasc. (24 p.) 225 2 $aPuntolinea$iAttualitą Normativa$v89 410 0$12001$aPuntolinea$iAttualitą Normativa$v89 454 1 $12001 461 1$1001------$12001 606 0 $aConcessione edilizia in sanatoria 676 $a346.45045 700 1$aFIORE,$bGiovanni$0357697 701 1$aCLASER,$bAntonio$0501937 801 0$aIT$bsalbc$gISBD 912 $a990002401280203316 951 $aXXX.A. Coll. 80/ 30 (COLL PIC 89)$b44578 G$cXXX.A. Coll. 80/ 30 (COLL PIC)$d00123763 959 $aBK 969 $aGIU 979 $aACQUISTI$b10$c20050221$lUSA01$h1234 979 $aIANNONE$b90$c20050429$lUSA01$h1446 979 $aIANNONE$b90$c20050502$lUSA01$h1636 979 $aRSIAV2$b90$c20100104$lUSA01$h1055 996 $aCondono, concordato, preventivo$91065654 997 $aUNISA LEADER 05781nam 22007094a 450 001 9910784654603321 005 20230120004635.0 010 $a1-280-96684-X 010 $a9786610966844 010 $a0-08-047479-9 035 $a(CKB)1000000000364094 035 $a(EBL)288757 035 $a(OCoLC)162573568 035 $a(SSID)ssj0000078591 035 $a(PQKBManifestationID)11188502 035 $a(PQKBTitleCode)TC0000078591 035 $a(PQKBWorkID)10061704 035 $a(PQKB)11413068 035 $a(Au-PeEL)EBL288757 035 $a(CaPaEBR)ebr10169928 035 $a(CaONFJC)MIL96684 035 $a(CaSebORM)9780123705976 035 $a(MiAaPQ)EBC288757 035 $a(EXLCZ)991000000000364094 100 $a20060227d2006 uy 0 101 0 $aeng 135 $aurunu||||| 181 $ctxt 182 $cc 183 $acr 200 00$aVLSI test principles and architectures$b[electronic resource] $edesign for testability /$fedited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen 205 $a1st edition 210 $aAmsterdam ;$aBoston $cElsevier Morgan Kaufmann Publishers$dc2006 215 $a1 online resource (809 p.) 225 1 $aThe Morgan Kaufmann series in systems on silicon 300 $aDescription based upon print version of record. 311 $a1-4933-0086-5 311 $a0-12-370597-5 320 $aIncludes bibliographical references and index. 327 $aFront cover; Title page; Copyright page; Table of contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; 1 Introduction; Importance of Testing; Testing During the VLSI Lifecycle; VLSI Development Process; Design Verification; Yield and Reject Rate; Electronic System Manufacturing Process; System-Level Operation; Challenges in VLSI Testing; Test Generation; Fault Models; Stuck-At Faults; Transistor Faults; Open and Short Faults; Delay Faults and Crosstalk; Pattern Sensitivity and Coupling Faults; Analog Fault Models; Levels of Abstraction in VLSI Testing 327 $aRegister-Transfer Level and Behavioral Level Gate Level; Switch Level; Physical Level; Historical Review of VLSI Test Technology; Automatic Test Equipment; Automatic Test Pattern Generation; Fault Simulation; Digital Circuit Testing; Analog and Mixed-Signal Circuit Testing; Design for Testability; Board Testing; Boundary Scan Testing; Concluding Remarks; Exercises; Acknowledgments; References; 2 Design for Testability; Introduction; Testability Analysis; SCOAP Testability Analysis; Combinational Controllability and Observability Calculation 327 $aSequential Controllability and Observability Calculation Probability-Based Testability Analysis; Simulation-Based Testability Analysis; RTL Testability Analysis; Design for Testability Basics; Ad Hoc Approach; Test Point Insertion; Structured Approach; Scan Cell Designs; Muxed-D Scan Cell; Clocked-Scan Cell; LSSD Scan Cell; Scan Architectures; Full-Scan Design; Muxed-D Full-Scan Design; Clocked Full-Scan Design; LSSD Full-Scan Design; Partial-Scan Design; Random-Access Scan Design; Scan Design Rules; Tristate Buses; Bidirectional I/O Ports; Gated Clocks; Derived Clocks 327 $aCombinational Feedback Loops Asynchronous Set/Reset Signals; Scan Design Flow; Scan Design Rule Checking and Repair; Scan Synthesis; Scan Configuration; Scan Replacement; Scan Reordering; Scan Stitching; Scan Extraction; Scan Verification; Verifying the Scan Shift Operation; Verifying the Scan Capture Operation; Scan Design Costs; Special-Purpose Scan Designs; Enhanced Scan; Snapshot Scan; Error-Resilient Scan; RTL Design for Testability; RTL Scan Design Rule Checking and Repair; RTL Scan Synthesis; RTL Scan Extraction and Scan Verification; Concluding Remarks; Exercises; Acknowledgments 327 $aReferences 3 Logic and Fault Simulation; Introduction; Logic Simulation for Design Verification; Fault Simulation for Test and Diagnosis; Simulation Models; Gate-Level Network; Sequential Circuits; Logic Symbols; Unknown State u; High-Impedance State Z; Intermediate Logic States; Logic Element Evaluation; Truth Tables; Input Scanning; Input Counting; Parallel Gate Evaluation; Timing Models; Transport Delay; Inertial Delay; Wire Delay; Functional Element Delay Model; Logic Simulation; Compiled-Code Simulation; Logic Optimization; Logic Levelization; Code Generation; Event-Driven Simulation 327 $aNominal-Delay Event-Driven Simulation 330 $aThis book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.· Most up-to-date coverage of design for testability. · Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. · Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.· Lecture slides and exercise solutions for all chapters are now available.· 410 0$aMorgan Kaufmann series in systems on silicon. 606 $aIntegrated circuits$xVery large scale integration$xTesting 606 $aIntegrated circuits$xVery large scale integration$xDesign 615 0$aIntegrated circuits$xVery large scale integration$xTesting. 615 0$aIntegrated circuits$xVery large scale integration$xDesign. 676 $a621.39/5 701 $aWang$b Laung-Terng$01497154 701 $aWu$b Cheng-Wen$cEE Ph. D.$01497155 701 $aWen$b Xiaoqing$01497156 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910784654603321 996 $aVLSI test principles and architectures$93722206 997 $aUNINA