LEADER 05579nam 2200673 a 450 001 9910782360203321 005 20210512085735.0 010 $a1-282-28512-2 010 $a9786612285127 010 $a0-08-056885-8 035 $a(CKB)1000000000547618 035 $a(EBL)452921 035 $a(OCoLC)281596147 035 $a(SSID)ssj0000074490 035 $a(PQKBManifestationID)11123473 035 $a(PQKBTitleCode)TC0000074490 035 $a(PQKBWorkID)10118812 035 $a(PQKB)11746221 035 $a(Au-PeEL)EBL452921 035 $a(CaPaEBR)ebr10329433 035 $a(CaONFJC)MIL228512 035 $a(CaSebORM)9780120887859 035 $a(MiAaPQ)EBC452921 035 $a(EXLCZ)991000000000547618 100 $a20080310d2008 uy 0 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 14$aThe designer's guide to VHDL /$fPeter J. Ashenden 205 $a3rd ed. 210 1$aAmsterdam :$cMorgan Kaufmann Publishers,$d[2008] 215 $a1 online resource (933 pages) 225 1 $aThe Morgan Kaufmann series in systems on silicon 300 $aDescription based upon print version of record. 311 $a0-12-088785-1 320 $aIncludes bibliographical references (p. 889-890) and index. 327 $aFront Cover; The Designer's Guide to VHDL; Copyright Page; Contents; Preface; Chapter 1. Fundamental Concepts; 1.1 Modeling Digital Systems; 1.2 Domains and Levels of Modeling; 1.3 Modeling Languages; 1.4 VHDL Modeling Concepts; 1.5 Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types and Operations; 2.1 Constants and Variables; 2.2 Scalar Types; 2.3 Type Classification; 2.4 Attributes of Scalar Types; 2.5 Expressions and Predefined Operations; Exercises; Chapter 3. Sequential Statements; 3.1 If Statements; 3.2 Case Statements; 3.3 Null Statements 327 $a3.4 Loop Statements3.5 Assertion and Report Statements; Exercises; Chapter 4. Composite Data Types and Operations; 4.1 Arrays; 4.2 Unconstrained Array Types; 4.3 Array Operations and Referencing; 4.4 Records; Exercises; Chapter 5. Basic Modeling Constructs; 5.1 Entity Declarations and Architecture Bodies; 5.2 Behavioral Descriptions; 5.3 Structural Descriptions; 5.4 Design Processing; Exercises; Chapter 6. Subprograms; 6.1 Procedures; 6.2 Procedure Parameters; 6.3 Concurrent Procedure Call Statements; 6.4 Functions; 6.5 Overloading; 6.6 Visibility of Declarations; Exercises 327 $aChapter 7. Packages and Use Clauses7.1 Package Declarations; 7.2 Package Bodies; 7.3 Use Clauses; Exercises; Chapter 8. Resolved Signals; 8.1 Basic Resolved Signals; 8.2 Resolved Signals, Ports, and Parameters; Exercises; Chapter 9. Predefined and Standard Packages; 9.1 The Predefined Packages standard and env; 9.2 IEEE Standard Packages; Exercises; Chapter 10 Case Study: A Pipelined Multiplier Accumulator; 10.1 Algorithm Outline; 10.2 A Behavioral Model; 10.3 A Register-Transfer-Level Model; Exercises; Chapter 11. Aliases; 11.1 Aliases for Data Objects; 11.2 Aliases for Non-Data Items 327 $aExercisesChapter 12. Generics; 12.1 Generic Constants; 12.2 Generic Types; 12.3 Generic Lists in Packages; 12.4 Generic Lists in Subprograms; 12.5 Generic Subprograms; 12.6 Generic Packages; Exercises; Chapter 13. Components and Configurations; 13.1 Components; 13.2 Configuring Component Instances; 13.3 Configuration Specifications; Exercises; Chapter 14. Generate Statements; 14.1 Generating Iterative Structures; 14.2 Conditionally Generating Structures; 14.3 Configuration of Generate Statements; Exercises; Chapter 15. Access Types; 15.1 Access Types; 15.2 Linked Data Structures 327 $a15.3 An Ordered-Dictionary ADT Using Access TypesExercises; Chapter 16. Files and Input/Output; 16.1 Files; 16.2 The Package Textio; Exercises; Chapter 17. Case Study: A Package for Memories; 17.1 The Memories Package; 17.2 Using the Memories Package; Exercises; Chapter 18. Test Bench and Verification Features; 18.1 External Names; 18.2 Force and Release Assignments; 18.3 Embedded PSL in VHDL; Exercises; Chapter 19. Shared Variables and Protected Types; 19.1 Shared Variables and Mutual Exclusion; 19.2 Uninstantiated Methods in Protected Types; Exercises; Chapter 20. Attributes and Groups 327 $a20.1 Predefined Attributes 330 $aVHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.* First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard...helps readers get up to speed quickly with new features of the new standard.* Presents a structured guide to t 410 0$aMorgan Kaufmann series in systems on silicon. 606 $aVHDL (Computer hardware description language) 606 $aElectronic digital computers$xComputer simulation 615 0$aVHDL (Computer hardware description language) 615 0$aElectronic digital computers$xComputer simulation. 676 $a621.39/2 700 $aAshenden$b Peter J$062474 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910782360203321 996 $aDesigner's guide to VHDL$9374700 997 $aUNINA