LEADER 04213nam 22005173u 450 001 9910780159503321 005 20220607174345.0 010 $a1-58053-471-6 035 $a(CKB)111056486960462 035 $a(EBL)257584 035 $a(OCoLC)475973986 035 $a(SSID)ssj0000254954 035 $a(PQKBManifestationID)11216358 035 $a(PQKBTitleCode)TC0000254954 035 $a(PQKBWorkID)10212712 035 $a(PQKB)11467307 035 $a(MiAaPQ)EBC257584 035 $a(EXLCZ)99111056486960462 100 $a20130418d2006|||| u|| | 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aSystem-on-a-chip$b[electronic resource] $edesign and test 210 $aNorwood $cArtech House$d2006 215 $a1 online resource (289 p.) 300 $aDescription based upon print version of record. 311 $a1-58053-107-5 327 $aContents v; Preface xi; Acknowledgment xiii; 1 Introduction 3; 1.1 Architecture of the Present-Day SoC 5; 1.2 Design Issues of SoC 8; 1.3 Hardware-Software Codesign 14; 1.4 Core Libraries, EDA Tools, and Web Pointers 21; References 29; 2 Design Methodology for Logic Cores 33; 2.1 SoC Design Flow 34; 2.2 General Guidelines for Design Reuse 36; 2.3 Design Process for Soft and Firm Cores 43; 2.4 Design Process for Hard Cores 47; 2.5 Sign-Off Checklist and Deliverables 51; 2.6 System Integration 53; References 55; 3 Design Methodology for Memory and Analog Cores 57 327 $a3.1 Why Large Embedded Memories 573.2 Design Methodology for Embedded Memories 59; 3.3 Specifications of Analog Circuits 72; 3.4 High-Speed Circuits 79; References 83; 4 Design Validation 85; 4.1 Core-Level Validation 86; 4.2 Core Interface Verification 93; 4.3 SoC Design Validation 95; Reference 103; 5 Core and SoC Design Examples 105; 5.1 Microprocessor Cores 105; 5.2 Comments on Memory Core Generators 112; 5.3 Core Integration and On-Chip Bus 113; 5.4 Examples of SoC 115; References 122; 6 Testing of Digital Logic Cores 125; 6.1 SoC Test Issues 126 327 $a6.2 Access, Control, and Isolation 1286.3 IEEE P1500 Effort 129; 6.4 Core Test and IP Protection 138; 6.5 Test Methodology for Design Reuse 142; 6.6 Testing of Microprocessor Cores 144; References 152; 7 Testing of Embedded Memories 155; 7.1 Memory Fault Models and Test Algorithms 156; 7.2 Test Methods for Embedded Memories 162; 7.3 Memory Redundancy and Repair 171; 7.4 Error Detection and Correction Codes 175; 7.5 Production Testing of SoC With Large Embedded Memory 176; References 177; 8 Testing of Analog and Mixed-Signal Cores 181 327 $a8.1 Analog Parameters and Characterization 1828.2 Design-for-Test and Built-in Self-Test Methods for Analog Cores 191; 8.3 Testing of Specific Analog Circuits 200; References 204; 9 Iddq Testing 207; 9.1 Physical Defects 207; 9.2 Iddq Testing Difficulties in SoC 219; 9.3 Design-for-Iddq-Testing 115; 9.4 Design Rules for Iddq Testing 230; 9.5 Iddq Test Vector Generation 231; References 236; 10 Production Testing 239; 10.1 Production Test Flow 239; 10.2 At-Speed Testing 241; 10.3 Production Throughput and Material Handling 246; References 249 327 $a11 Summary and Conclusions 25111.1 Summary 251; 11.2 Future Scenarios 254; Appendix: RTL Guidelines for Design Reuse 257; A.1 Naming Convention 257; A.2 General Coding Guidelines 258; A.3 RTL Development for Synthesis 260; A.4 RTL Checks 262; About the Author 265; Index 267 330 $aStarting with a basic overview of system-on-a-chip (SoC) including definitions of related terms, this text explains SoC design challenges, together with developments in SoC design and test methodologies. 606 $aEmbedded computer systems - Design and construction 615 4$aEmbedded computer systems - Design and construction. 676 $a621.395 700 $aRajsuman$b Rochit$01545282 801 0$bAU-PeEL 801 1$bAU-PeEL 801 2$bAU-PeEL 906 $aBOOK 912 $a9910780159503321 996 $aSystem-on-a-chip$93800150 997 $aUNINA