LEADER 00799nam2-22002891i-450- 001 990000390050403321 005 20070507100123.0 035 $a000039005 035 $aFED01000039005 035 $a(Aleph)000039005FED01 035 $a000039005 100 $a20020821d1927----km-y0itay50------ba 101 0 $aita 105 $ay-------001yy 200 1 $a<>Messanalyse. Teil 1$fVon I.M. Kolthoff. 210 $aBerlin$cVerlag von Springer$d1927 215 $a2 voll., 24 cm 461 0$1001000030479$12001$aDie Massanalyse$v1-2 676 $a545 700 1$aKolthoff,$bI.-M.$022250 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990000390050403321 952 $a04 081-47/1$bCI 0766$fDINCH 959 $aDINCH 996 $aMessanalyse. Teil 1$9135217 997 $aUNINA LEADER 03519nam 22005895 450 001 9910760263503321 005 20250807132312.0 010 $a3-031-37989-6 024 7 $a10.1007/978-3-031-37989-5 035 $a(MiAaPQ)EBC30751939 035 $a(Au-PeEL)EBL30751939 035 $a(DE-He213)978-3-031-37989-5 035 $a(PPN)272740853 035 $a(CKB)28283991300041 035 $a(EXLCZ)9928283991300041 100 $a20230922d2024 u| 0 101 0 $aeng 135 $aurcnu|||||||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aUnderstanding Logic Locking /$fby Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor 205 $a1st ed. 2024. 210 1$aCham :$cSpringer International Publishing :$cImprint: Springer,$d2024. 215 $a1 online resource (385 pages) 311 08$aPrint version: Zamiri Azar, Kimia Understanding Logic Locking Cham : Springer International Publishing AG,c2023 9783031379888 327 $aBasics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP. 330 $aThis book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO?s and DON?Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking. Covers modern VLSI design, testability and debug, and hardware security threats at different levels of abstraction; Provides a comprehensive overview of logic locking techniques and their applications to hardware security; Covers logic locking from implementation to evaluation, different assumptions, models and abstraction layers. 606 $aElectronic circuit design 606 $aEmbedded computer systems 606 $aElectronic circuits 606 $aElectronics Design and Verification 606 $aEmbedded Systems 606 $aElectronic Circuits and Systems 615 0$aElectronic circuit design. 615 0$aEmbedded computer systems. 615 0$aElectronic circuits. 615 14$aElectronics Design and Verification. 615 24$aEmbedded Systems. 615 24$aElectronic Circuits and Systems. 676 $a005.8 700 $aZamiri Azar$b Kimia$01438734 701 $aMardani Kamali$b Hadi$01438735 701 $aFarahmandi$b Farimah$0977878 701 $aTehranipoor$b Mohammad H.$f1974-$01350630 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910760263503321 996 $aUnderstanding Logic Locking$94489055 997 $aUNINA