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010   $a1-4614-6759-4
024 7 $a10.1007/978-1-4614-6759-5
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035   $a(EBL)1697822
035   $a(OCoLC)902411610
035   $a(SSID)ssj0000905947
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035   $a(PQKBTitleCode)TC0000905947
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035   $a(DE-He213)978-1-4614-6759-5
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035   $a(PPN)169136647
035   $a(EXLCZ)992560000000102855
100   $a20130430d2013      u|             0
101 0 $aeng
135   $aur|n|---|||||
181   $ctxt
182   $cc
183   $acr
200 10$a3D Video Coding for Embedded Devices$b[electronic resource] $eEnergy Efficient Algorithms and Architectures /$fby Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel
205   $a1st ed. 2013.
210  1$aNew York, NY :$cSpringer New York :$cImprint: Springer,$d2013.
215   $a1 online resource (219 p.)
300   $aDescription based upon print version of record.
311   $a1-4614-6758-6 
320   $aIncludes bibliographical references and index.
327   $aIntroduction -- Background and Related Work -- Multiview Video Coding Analysis for Energy and Quality -- Energy-Effiecient Algorithms for Multiview Video Coding -- Energy-Efficient Architectures for Multiview Video Coding -- Results and Comparison -- Conclusion and future Works.
330   $aThis book shows readers how to develop energy-efficient algorithms and hardware architectures to enable high-definition 3D video coding on resource-constrained embedded devices.  Users of the Multiview Video Coding (MVC) standard face the challenge of exploiting its 3D video-specific coding tools for increasing compression efficiency at the cost of increasing computational complexity and, consequently, the energy consumption.  This book enables readers to reduce the multiview video coding energy consumption through jointly considering the algorithmic and architectural levels.  Coverage includes an introduction to 3D videos and an extensive discussion of the current state-of-the-art of 3D video coding, as well as energy-efficient algorithms for 3D video coding and energy-efficient hardware architecture for 3D video coding.     ·         Discusses challenges related to performance and power in 3D video coding for embedded devices; ·         Describes energy-efficient algorithms for reducing computational complexity at multiple hierarchical levels; ·         Presents energy-efficient hardware architectures along with methods for reducing on-chip and off-chip energy related to both data processing and memory access; ·         Shows how to leverage jointly the algorithm and hardware architecture layers of the system.
606   $aElectronic circuits
606   $aElectronics
606   $aMicroelectronics
606   $aMicroprocessors
606   $aCircuits and Systems$3https://scigraph.springernature.com/ontologies/product-market-codes/T24068
606   $aElectronics and Microelectronics, Instrumentation$3https://scigraph.springernature.com/ontologies/product-market-codes/T24027
606   $aProcessor Architectures$3https://scigraph.springernature.com/ontologies/product-market-codes/I13014
615  0$aElectronic circuits.
615  0$aElectronics.
615  0$aMicroelectronics.
615  0$aMicroprocessors.
615 14$aCircuits and Systems.
615 24$aElectronics and Microelectronics, Instrumentation.
615 24$aProcessor Architectures.
676   $a004.1
676   $a006.22
676   $a620
676   $a621.381
700   $aZatt$b Bruno$4aut$4http://id.loc.gov/vocabulary/relators/aut$01424567
702   $aShafique$b Muhammad$4aut$4http://id.loc.gov/vocabulary/relators/aut
702   $aBampi$b Sergio$4aut$4http://id.loc.gov/vocabulary/relators/aut
702   $aHenkel$b Jörg$4aut$4http://id.loc.gov/vocabulary/relators/aut
906   $aBOOK
912   $a9910739446903321
996   $a3D Video Coding for Embedded Devices$93553863
997   $aUNINA