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010   $a3-031-34237-2
024 7 $a10.1007/978-3-031-34237-0
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035   $a(Au-PeEL)EBL30668268
035   $a(DE-He213)978-3-031-34237-0
035   $a(PPN)272257222
035   $a(CKB)27867643500041
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100   $a20230727d2023      u|         0
101 0 $aeng
135   $aurcnu||||||||
181   $ctxt$2rdacontent
182   $cc$2rdamedia
183   $acr$2rdacarrier
200 10$aOn-Chip Training NPU - Algorithm, Architecture and SoC Design /$fby Donghyeon Han, Hoi-Jun Yoo
205   $a1st ed. 2023.
210  1$aCham :$cSpringer Nature Switzerland :$cImprint: Springer,$d2023.
215   $a1 online resource (249 pages)
311 08$aPrint version: Han, Donghyeon On-Chip Training NPU - Algorithm, Architecture and SoC Design Cham : Springer,c2023 9783031342363 
327   $aChapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion.
330   $aUnlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding.
606   $aElectronic circuits
606   $aEmbedded computer systems
606   $aMicroprocessors
606   $aComputer architecture
606   $aElectronic Circuits and Systems
606   $aEmbedded Systems
606   $aProcessor Architectures
615  0$aElectronic circuits.
615  0$aEmbedded computer systems.
615  0$aMicroprocessors.
615  0$aComputer architecture.
615 14$aElectronic Circuits and Systems.
615 24$aEmbedded Systems.
615 24$aProcessor Architectures.
676   $a621.3815
700   $aHan$b Donghyeon$01380380
701   $aYoo$b Hoi-Jun$01380381
801  0$bMiAaPQ
801  1$bMiAaPQ
801  2$bMiAaPQ
906   $aBOOK
912   $a9910736029603321
996   $aOn-Chip Training NPU - Algorithm, Architecture and SoC Design$93421645
997   $aUNINA