LEADER 03690nam 22005775 450 001 9910734868403321 005 20230713134339.0 010 $a3-031-33136-2 024 7 $a10.1007/978-3-031-33136-7 035 $a(CKB)27588306700041 035 $a(DE-He213)978-3-031-33136-7 035 $a(MiAaPQ)EBC30645938 035 $a(Au-PeEL)EBL30645938 035 $a(PPN)272256994 035 $a(EXLCZ)9927588306700041 100 $a20230713d2023 u| 0 101 0 $aeng 135 $aurnn|008mamaa 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aEfficient Execution of Irregular Dataflow Graphs$b[electronic resource] $eHardware/Software Co-optimization for Probabilistic AI and Sparse Linear Algebra /$fby Nimish Shah, Wannes Meert, Marian Verhelst 205 $a1st ed. 2023. 210 1$aCham :$cSpringer Nature Switzerland :$cImprint: Springer,$d2023. 215 $a1 online resource (XXI, 143 p. 1 illus.) 311 $a9783031331350 327 $aChapter 1. Irregular workloads at risk of losing the hardware lottery -- Chapter 2. Suitable data representation: A study of fixed point, floating point,and positTM formats for probabilistic AI -- Chapter 3. GraphOpt: constrained-optimization-based parallelization of irregular workloads for multicore processors -- Chapter 4. DAG Processing Unit version 1 (DPU): Efficient execution of irregular workloads on a multicore processor -- Chapter 5. DAG Processing Unit version 2 (DPU-v2): Efficient execution of irregular workloads on a spatial datapath -- Chapter 6. Conclusions and future work. 330 $aThis book focuses on the acceleration of emerging irregular sparse workloads, posed by novel artificial intelligent (AI) models and sparse linear algebra. Specifically, the book outlines several co-optimized hardware-software solutions for a highly promising class of emerging sparse AI models called Probabilistic Circuit (PC) and a similar sparse matrix workload for triangular linear systems (SpTRSV). The authors describe optimizations for the entire stack, targeting applications, compilation, hardware architecture and silicon implementation, resulting in orders of magnitude higher performance and energy-efficiency compared to the existing state-of-the-art solutions. Thus, this book provides important building blocks for the upcoming generation of edge AI platforms. Analyzes the key bottlenecks in the existing platforms for these sparse and irregular AI and linear algebra algorithms; Discusses an emerging set of AI workloads that rely on sparse matrix operations and graph-based computations; Shows how to address the execution challenges of this novel class of algorithms through hardware-software codesign. 606 $aElectronic circuits 606 $aEmbedded computer systems 606 $aMachine learning 606 $aElectronic Circuits and Systems 606 $aEmbedded Systems 606 $aMachine Learning 615 0$aElectronic circuits. 615 0$aEmbedded computer systems. 615 0$aMachine learning. 615 14$aElectronic Circuits and Systems. 615 24$aEmbedded Systems. 615 24$aMachine Learning. 676 $a621.3815 700 $aShah$b Nimish$4aut$4http://id.loc.gov/vocabulary/relators/aut$01428342 702 $aMeert$b Wannes$4aut$4http://id.loc.gov/vocabulary/relators/aut 702 $aVerhelst$b Marian$4aut$4http://id.loc.gov/vocabulary/relators/aut 801 0$bMiAaPQ 801 1$bMiAaPQ 801 2$bMiAaPQ 906 $aBOOK 912 $a9910734868403321 996 $aEfficient Execution of Irregular Dataflow Graphs$93564205 997 $aUNINA