LEADER 00851nam0-22003131i-450- 001 990005298800403321 005 20050719132118.0 035 $a000529880 035 $aFED01000529880 035 $a(Aleph)000529880FED01 035 $a000529880 100 $a19990604d1969----km-y0itay50------ba 101 0 $afre 105 $ay-------001yy 200 1 $a<>Coran$fpar Règis Blachère 205 $a2. Td. 210 $aParis$cPresses Universitaires de France$d1969 215 $a126 p.$d18 cm 225 1 $aQue sais-je?$v1245 610 0 $aCORANO 676 $a297.122$v21$zita 700 1$aBlachère,$bRégis$f<1900-1973>$0417321 801 0$aIT$bUNINA$gRICA$2UNIMARC 901 $aBK 912 $a990005298800403321 952 $a297.122 BLA 3 (2. ed.)$bST.REL. 225$fFLFBC 959 $aFLFBC 996 $aCoran$9537129 997 $aUNINA LEADER 03975nam 2200637 450 001 9910455172203321 005 20200520144314.0 010 $a1-59693-384-4 035 $a(CKB)1000000000787510 035 $a(EBL)456885 035 $a(OCoLC)503447788 035 $a(SSID)ssj0000137235 035 $a(PQKBManifestationID)11144685 035 $a(PQKBTitleCode)TC0000137235 035 $a(PQKBWorkID)10087805 035 $a(PQKB)10699572 035 $a(MiAaPQ)EBC456885 035 $a(Au-PeEL)EBL456885 035 $a(CaPaEBR)ebr10312962 035 $a(OCoLC)535923707 035 $a(CaBNVSL)mat09100660 035 $a(IEEE)9100660 035 $a(EXLCZ)991000000000787510 100 $a20200730d2008 uy 101 0 $aeng 135 $aur|n|---||||| 181 $ctxt 182 $cc 183 $acr 200 10$aDesign methodology for RF CMOS phase locked loops /$fCarlos Quemada, Guillermo Bistue?, Ia?nigo Adin 210 1$aBoston :$cArtech House,$d©2009. 210 2$a[Piscataqay, New Jersey] :$cIEEE Xplore,$d[2008] 215 $a1 online resource (242 p.) 225 1 $aArtech House microwave library 300 $aDescription based upon print version of record. 311 $a1-59693-383-6 320 $aIncludes bibliographical references and index. 327 $aDesign Methodology for RF CMOS Phase Locked Loops; Contents; Preface; 1 Approach to CMOS PLL Design; 2 PLL Fundamentals; 3 LC-Tank Integrated Oscillators; 4 Frequency Divider; 5 Phase Frequency Detector/Phase Detector; 6 Determination of Building Blocks Specifications; 7 Design of a 3.2-GHz CMOS VCO; 8 Design of a Frequency Divider; 9 Design of a Phase Frequency Detector; 10 Design of the Complete PLL; 11 PLL Characterization and Results; About the Authors; Index 330 3 $aBlast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications.$cPublisher abstract. 410 0$aArtech House microwave library. 606 $aMetal oxide semiconductors, Complementary$xDesign and construction 606 $aPhase-locked loops$xDesign and construction 608 $aElectronic books. 615 0$aMetal oxide semiconductors, Complementary$xDesign and construction. 615 0$aPhase-locked loops$xDesign and construction. 676 $a621.3815/364 700 $aQuemada$b Carlos$0857502 701 $aBistue?$b Guillermo$0857503 701 $aAdin$b Ia?nigo$0857504 801 0$bCaBNVSL 801 1$bCaBNVSL 801 2$bCaBNVSL 906 $aBOOK 912 $a9910455172203321 996 $aDesign methodology for RF CMOS phase locked loops$91914743 997 $aUNINA LEADER 01896oam 2200469 450 001 9910705749803321 005 20171206132111.0 035 $a(CKB)5470000002452909 035 $a(OCoLC)990787558 035 $a(EXLCZ)995470000002452909 100 $a20170622d2017 ua 0 101 0 $aeng 135 $aurbn||||a|||| 181 $ctxt$2rdacontent 182 $cc$2rdamedia 183 $acr$2rdacarrier 200 10$aAssessing TSA's management and implementation of the Screening Partnership Program $ehearing before the Subcommittee on Transportation Security of the Committee on Homeland Security, House of Representatives, One Hundred Fourteenth Congress, first session, November 17, 2015 210 1$aWashington :$cU.S. Government Publishing Office,$d2017. 215 $a1 online resource (iii, 38 pages) $cillustrations 300 $aPaper version available for sale by the Superintendent of Documents, United States Government Publishing Office. 300 $a"Serial No. 114-44." 320 $aIncludes bibliographical references. 517 $aAssessing TSA's management and implementation of the Screening Partnership Program 606 $aAirline passenger security screening$zUnited States 606 $aAirports$xBaggage handling$xSecurity measures$zUnited States 606 $aAirports$xSecurity measures$zUnited States 608 $aLegislative hearings.$2lcgft 615 0$aAirline passenger security screening 615 0$aAirports$xBaggage handling$xSecurity measures 615 0$aAirports$xSecurity measures 801 0$bGPO 801 1$bGPO 801 2$bGPO 801 2$bAZP 801 2$bMERUC 801 2$bOCLCQ 801 2$bOCLCO 801 2$bGPO 906 $aBOOK 912 $a9910705749803321 996 $aAssessing TSA's management and implementation of the Screening Partnership Program$93497615 997 $aUNINA